US6774687B2
Expired / Lapsed
US
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Method and apparatus for characterizing a delay locked loop
Assignee: Micron Technology Inc
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Filing: 2002-03-11
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Granted: 2004-08-10
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Expires: 2022-03-11
Abstract
Abstract A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal. The feedback path is configured to provide a feedback clock signal based on the output clock signal. The phase detector is configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal. The logic is coupled to the delay line and configured to receive the shift signal and control the time interval based on the shift signal. The dither circuit is coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal.
Inventors
- 👤 Tyler J. Gomm
- 👤 Michael B. Roth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:57
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816
Claims Analysis
Total Claims: 112
Claim 1
Independent Claim
134 words
A delay locked loop, comprising: a forward path including a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal; a feedback path configured to provide a feedback clock signal based on the output clock signal; a phase detector configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to the delay line configured to introduce a variable delay responsive to an assertion of a test mode enable signal.
Claim 2
Dependent Claim
134 words
A delay locked loop, comprising: a forward path including a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal; a feedback path configured to provide a feedback clock signal based on the output clock signal; a phase detector configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to the delay line configured to introduce a variable delay responsive to an assertion of a test mode enable signal.
Claim 3
Dependent Claim
18 words
The delay locked loop of claim 1 , wherein the dither circuit is coupled to the forward path.
Claim 4
Dependent Claim
18 words
The delay locked loop of claim 1 , wherein the dither circuit is coupled to the feedback path.
Claim 5
Dependent Claim
17 words
The delay locked loop of claim 1 , wherein the variable delay comprises a periodic variable delay.
Claim 6
Dependent Claim
17 words
The delay locked loop of claim 4 , wherein the periodic variable delay has a triangular waveform.
Claim 7
Dependent Claim
17 words
The delay locked loop of claim 4 , wherein the periodic variable delay has a sawtooth waveform.
Claim 8
Dependent Claim
39 words
The delay locked loop of claim 1 , wherein the dither circuit further comprises: a plurality of delay elements; and dither control logic configured to selectively enable at least a portion of the delay elements to generate the delay.
Claim 9
Dependent Claim
17 words
The delay locked loop of claim 7 , wherein the dither control logic further comprises a counter.
Claim 10
Dependent Claim
18 words
The delay locked loop of claim 7 , wherein the dither control logic further comprises an up/down counter.
Claim 11
Dependent Claim
16 words
The delay locked loop of claim 7 , wherein the plurality of delay elements comprise capacitors.
Claim 12
Dependent Claim
17 words
The delay locked loop of claim 10 , wherein the capacitors have essentially the same capacitance values.
Claim 13
Dependent Claim
37 words
The delay locked loop of claim 7 , wherein the dither control logic further comprises a counter having a plurality of stages, and the plurality of delay elements comprise capacitors enabled by the stages of the counter.
Claim 14
Dependent Claim
33 words
The delay locked loop of claim 12 , wherein the capacitors comprise weighted capacitors, each weighted capacitor having a weighted capacitance based on the stage of the counter by which it is enabled.
Claim 15
Dependent Claim
41 words
The delay locked loop of claim 13 , wherein, for a stage k of the counter, its associated weighted capacitor has a capacitance of 2 k times a capacitance of the weighted capacitor associated with a first stage of the counter.
Claim 16
Dependent Claim
34 words
The delay locked loop of claim 12 , wherein the capacitors comprise banks of capacitors, each bank having an associated weighted capacitance based on the stage of the counter by which it is enabled.
Claim 17
Dependent Claim
43 words
The delay locked loop of claim 15 , wherein, for a stage k of the counter, its associated bank of capacitors has a capacitance of 2 k times a capacitance of the bank of capacitors associated with a first stage of the counter.
Claim 18
Dependent Claim
32 words
The delay locked loop of claim 7 , wherein the dither control logic further comprises a counter, and the plurality of delay elements comprise capacitors sequentially enabled by increments of the counter.
Claim 19
Dependent Claim
34 words
The delay looked loop of claim 7 , wherein the dither control logic further comprises a shift register, and the plurality of delay elements comprise capacitors sequentially enabled by increments of the shift register.
Claim 20
Dependent Claim
47 words
The delay locked loop of claim 1 , further comprising a noise filter coupled to the phase detector and being configured to reduce noise in the shift signal, wherein the noise filter is configured to be disabled responsive to the assertion of the test mode enable signal.
Claim 21
Dependent Claim
45 words
The delay locked loop of claim 1 , further comprising a delay model coupled between the delay line and the feedback path, the delay model being configured to receive the output clock signal and delay the output clock signal to generate the feedback clock signal.
Claim 22
Independent Claim
173 words
A system, comprising: a first digital device configured to provide a first clock signal and a test mode enable signal; and a second digital device configured to receive the first clock signal and generate a second clock signal, the second digital device including: a forward path including a delay line configured to receive the first clock signal and delay the first clock signal by a time interval to generate the second clock signal; a feedback path configured to provide a feedback clock signal based on the second clock signal; a phase detector configured to compare the first clock signal and the feedback clock signal and generate a shift signal if the second clock signal is not in phase with the first clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to the delay line and configured to introduce a variable delay responsive to an assertion of a test mode enable signal.
Claim 23
Independent Claim
173 words
A system, comprising: a first digital device configured to provide a first clock signal and a test mode enable signal; and a second digital device configured to receive the first clock signal and generate a second clock signal, the second digital device including: a forward path including a delay line configured to receive the first clock signal and delay the first clock signal by a time interval to generate the second clock signal; a feedback path configured to provide a feedback clock signal based on the second clock signal; a phase detector configured to compare the first clock signal and the feedback clock signal and generate a shift signal if the second clock signal is not in phase with the first clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to the delay line and configured to introduce a variable delay responsive to an assertion of a test mode enable signal.
Claim 24
Dependent Claim
16 words
The system of claim 21 , wherein the dither circuit is coupled to the forward path.
Claim 25
Dependent Claim
16 words
The system of claim 21 , wherein the dither circuit is coupled to the feedback path.
Claim 26
Dependent Claim
15 words
The system of claim 21 , wherein the variable delay comprises a periodic variable delay.
Claim 27
Dependent Claim
15 words
The system of claim 24 , wherein the periodic variable delay has a triangular waveform.
Claim 28
Dependent Claim
15 words
The system of claim 24 , wherein the periodic variable delay has a sawtooth waveform.
Claim 29
Dependent Claim
31 words
The system of claim 23 , wherein the dither circuit further comprises: a plurality of delay elements; and dither control logic configured to enable selected delay elements to generate the delay.
Claim 30
Dependent Claim
15 words
The system of claim 27 , wherein the dither control logic further comprises a counter.
Claim 31
Dependent Claim
16 words
The system of claim 27 , wherein the dither control logic further comprises an up/down counter.
Claim 32
Dependent Claim
14 words
The system of claim 27 , wherein the plurality of delay elements comprise capacitors.
Claim 33
Dependent Claim
15 words
The system of claim 30 , wherein the capacitors have essentially the same capacitance values.
Claim 34
Dependent Claim
35 words
The system of claim 27 , wherein the dither control logic further comprises a counter having a plurality of stages, and the plurality of delay elements comprise capacitors enabled by the stages of the counter.
Claim 35
Independent Claim
31 words
The system of churn 32 , wherein the capacitors comprise weighted capacitors, each weighted capacitor having a weighted capacitance based on the stage of the counter by which it is enabled.
Claim 36
Independent Claim
31 words
The system of churn 32 , wherein the capacitors comprise weighted capacitors, each weighted capacitor having a weighted capacitance based on the stage of the counter by which it is enabled.
Claim 37
Dependent Claim
39 words
The system of claim 33 , wherein, for a stage k of the counter, its associated weighted capacitor has a capacitance of 2 k times a capacitance of the weighted capacitor associated with a first stage of the counter.
Claim 38
Dependent Claim
32 words
The system of claim 32 , wherein the capacitors comprise banks of capacitors, each bank having an associated weighted capacitance based on the stage of the counter by which it is enabled.
Claim 39
Dependent Claim
41 words
The system of claim 35 , wherein, for a stage k of the counter, its associated bank of capacitors has a capacitance of 2 k times a capacitance of the bank of capacitors associated with a first stage of the counter.
Claim 40
Dependent Claim
30 words
The system of claim 27 , wherein the dither control logic further comprises a counter, and the plurality of delay elements comprise capacitors sequentially enabled by increments of the counter.
Claim 41
Dependent Claim
32 words
The system of claim 27 , wherein the dither control logic further comprises a shift register, and the plurality of daisy elements comprise capacitors sequentially enabled by increments of the shift register.
Claim 42
Dependent Claim
45 words
The system of claim 21 , further comprising a noise filter coupled to the phase detector and being configured to reduce noise in the shift signal, wherein the noise filter is configured to be disabled responsive to the assertion of the test mode enable signal.
Claim 43
Dependent Claim
43 words
The system of claim 21 , further comprising a delay model coupled between the delay line and the feedback path, the delay model being configured to receive the second clock signal and delay the second clock signal to generate the feedback clock signal.
Claim 44
Dependent Claim
30 words
The system of claim 21 , wherein the first digital device is configured to perform a test of the second digital device while the teat mode enable signal is asserted.
Claim 45
Independent Claim
16 words
The system of chasm 21 , wherein the second digital device further comprises a memory device.
Claim 46
Independent Claim
16 words
The system of chasm 21 , wherein the second digital device further comprises a memory device.
Claim 47
Dependent Claim
15 words
The system of claim 42 , wherein the first digital device further comprises a microprocessor.
Claim 48
Independent Claim
235 words
A system, comprising: a first digital device configured to provide a first clock signal and a test mode enable signal; and a second digital device configured to receive the first clock signal and generate a second clock signal, the second digital device including: a forward path including a delay line configured to receive the first clock signal and delay the first clock signal by a time interval to generate the second clock signal; a feedback path configured to provide a feedback clock signal based on the second clock signal; a phase detector configured to compare the first clock signal and the feedback clock signal and generate a shift signal if the second clock signal is not in phase with the first clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal, wherein the first digital device is configured to perform a test of the second digital device while the test mode enable signal is asserted, the second digital device is configured to output a data signal synchronized with the second clock signal, and the first digital device is configured to measure a skew between transitions of the data signal and the first clock signal.
Claim 49
Independent Claim
235 words
A system, comprising: a first digital device configured to provide a first clock signal and a test mode enable signal; and a second digital device configured to receive the first clock signal and generate a second clock signal, the second digital device including: a forward path including a delay line configured to receive the first clock signal and delay the first clock signal by a time interval to generate the second clock signal; a feedback path configured to provide a feedback clock signal based on the second clock signal; a phase detector configured to compare the first clock signal and the feedback clock signal and generate a shift signal if the second clock signal is not in phase with the first clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal, wherein the first digital device is configured to perform a test of the second digital device while the test mode enable signal is asserted, the second digital device is configured to output a data signal synchronized with the second clock signal, and the first digital device is configured to measure a skew between transitions of the data signal and the first clock signal.
Claim 50
Dependent Claim
30 words
The system of claim 44 , wherein the first digital device is configured to determine an access time parameter, tAC, of the second digital device based on the measured skew.
Claim 51
Dependent Claim
32 words
The system of claim 45 , wherein the first digital device is configured to determine a minimum tAC and a maximum tAC of the second digital device based on the measured skew.
Claim 52
Dependent Claim
34 words
The system of claim 45 , wherein the first digital device is configured to indicate a fault condition associated with second digital device responsive to the determined tAC being greater that a design threshold.
Claim 53
Dependent Claim
17 words
The system of claim 44 , wherein the dither circuit is configured to generate a variable delay.
Claim 54
Dependent Claim
138 words
A delay locked loop, comprising: a forward path including a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal; a feedback path configured to provide a feedback clock signal based on the output clock signal; a phase detector configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to the delay line and the forward path and configured to introduce a delay responsive to an assertion of a test mode enable signal.
Claim 55
Dependent Claim
138 words
A delay locked loop, comprising: a forward path including a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal; a feedback path configured to provide a feedback clock signal based on the output clock signal; a phase detector configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to the delay line and the forward path and configured to introduce a delay responsive to an assertion of a test mode enable signal.
Claim 56
Independent Claim
88 words
A device, comprising: a delay locked loop having a forward path for receiving an input clock signal having a period and a feedback path for synchronizing the input clock signal with a feedback clock signal; and a dither circuit coupled to one of the forward path and the feedback path and being configured to introduce a variable delay to simulate an environmental variation in the delay locked loop responsive to a test mode enable signal, the variable delay being less than the period of the input clock signal.
Claim 57
Independent Claim
88 words
A device, comprising: a delay locked loop having a forward path for receiving an input clock signal having a period and a feedback path for synchronizing the input clock signal with a feedback clock signal; and a dither circuit coupled to one of the forward path and the feedback path and being configured to introduce a variable delay to simulate an environmental variation in the delay locked loop responsive to a test mode enable signal, the variable delay being less than the period of the input clock signal.
Claim 58
Dependent Claim
15 words
The device of claim 50 , wherein the variable delay comprises a periodic variable delay.
Claim 59
Dependent Claim
15 words
The device of claim 51 , wherein the periodic variable delay has a triangular waveform.
Claim 60
Dependent Claim
15 words
The device of claim 51 , wherein the periodic variable delay has a sawtooth waveform.
Claim 61
Dependent Claim
31 words
The device of claim 50 , wherein the dither circuit further comprises: a plurality of delay elements; and dither control logic configured to enable selected delay elements to generate the delay.
Claim 62
Dependent Claim
15 words
The device of claim 54 , wherein the dither control logic further comprises a counter.
Claim 63
Dependent Claim
16 words
The device of claim 54 , wherein the dither control logic further comprises an up/down counter.
Claim 64
Dependent Claim
14 words
The device of claim 54 , wherein the plurality of delay elements comprise capacitors.
Claim 65
Dependent Claim
15 words
The device of claim 57 , wherein the capacitors nave essentially the same capacitance values.
Claim 66
Dependent Claim
35 words
The device of claim 54 , wherein the dither control logic further comprises a counter having a plurality of stages, and the plurality of delay elements comprise capacitors enabled by the stages of the counter.
Claim 67
Dependent Claim
31 words
The device of claim 59 , wherein the capacitors comprise weighted capacitors, each weighted capacitor having a weighted capacitance based on the stage of the counter by which it is enabled.
Claim 68
Dependent Claim
39 words
The device of claim 60 , wherein, for a stage k of the counter, its associated weighted capacitor has a capacitance of 2 k times a capacitance of the weighted capacitor associated with a first stage of the counter.
Claim 69
Dependent Claim
32 words
The device of claim 59 , wherein the capacitors comprise banks of capacitors, each bank having an associated weighted capacitance based on the stage of the counter by which it is enabled.
Claim 70
Dependent Claim
41 words
The device of claim 62 , wherein, for a stage k of the counter, its associated bank of capacitors has a capacitance of 2 k times a capacitance of the bank of capacitors associated with a firs: stage of the counter.
Claim 71
Dependent Claim
30 words
The device of claim 54 , wherein the dither control logic further comprises a counter, and the plurality of delay elements comprise capacitors sequentially enabled by increments of the counter.
Claim 72
Dependent Claim
32 words
The device of claim 64 , wherein the dither control logic further comprises a shift register, and the plurality of delay elements comprise capacitors sequentially enabled by increments of the shift register.
Claim 73
Dependent Claim
35 words
The device of claim 50 , wherein the delay locked loop further comprises a noise filler, wherein the noise filter is configured to be disabled responsive to the assertion of the test mode enable signal.
Claim 74
Dependent Claim
189 words
A memory device, comprising: a forward path configured to receive an input clock signal; a data out line configured to output data from the memory device synchronized with an output clock signal; a test mode signal line configured to receive a test mode enable signal; and a delay line coupled to the forward path and configured to delay the input clock signal by a time interval to generate the output clock signal; a feedback path configured to provide a feedback clock signal based on the output clock signal; a phase detector configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the feedback clock signal is not in phase with the input clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to one of the forward path and the feedback path and configured to introduce a delay in one of the input clock signal and the feedback clock signal responsive to an assertion of a test mode enable signal.
Claim 75
Dependent Claim
189 words
A memory device, comprising: a forward path configured to receive an input clock signal; a data out line configured to output data from the memory device synchronized with an output clock signal; a test mode signal line configured to receive a test mode enable signal; and a delay line coupled to the forward path and configured to delay the input clock signal by a time interval to generate the output clock signal; a feedback path configured to provide a feedback clock signal based on the output clock signal; a phase detector configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the feedback clock signal is not in phase with the input clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to one of the forward path and the feedback path and configured to introduce a delay in one of the input clock signal and the feedback clock signal responsive to an assertion of a test mode enable signal.
Claim 76
Dependent Claim
18 words
The memory device of claim 67 , wherein the dither circuit is configured to generate a variable delay.
Claim 77
Dependent Claim
88 words
A methods comprising: receiving an input clock signal; delaying the input clock signal by a time interval to generate an output clock signal; receiving a feedback clock signal based on the output signal; detecting a phase alignment error between the input clock signal and the feedback clock signal; controlling the time interval to synchronize the input clock signal with the feedback clock signal; and introducing a periodic variable delay in one of the input clock signal and the feedback clock signal responsive to a test mode enable signal.
Claim 78
Dependent Claim
88 words
A methods comprising: receiving an input clock signal; delaying the input clock signal by a time interval to generate an output clock signal; receiving a feedback clock signal based on the output signal; detecting a phase alignment error between the input clock signal and the feedback clock signal; controlling the time interval to synchronize the input clock signal with the feedback clock signal; and introducing a periodic variable delay in one of the input clock signal and the feedback clock signal responsive to a test mode enable signal.
Claim 79
Dependent Claim
23 words
The method of claim 69 , wherein introducing the periodic variable delay further comprises introducing the periodic variable delay having a triangular waveform.
Claim 80
Dependent Claim
23 words
The method of claim 69 , wherein introducing the periodic variable delay further comprises introducing the periodic variable delay having a sawtooth waveform.
Claim 81
Independent Claim
128 words
A method, comprising: receiving an input clock signal; delaying the input clock signal by a time interval to generate an output clock signal; receiving a feedback clock signal based on the output signal; detecting a phase alignment error between the input clock signal and the feedback clock signal; controlling the lime interval to a synchronize the input clock signal with the feedback clock signal; and introducing a variable delay in one of the input clock signal and the feedback clock signal responsive to a test mode enable signal by: providing a plurality of capacitors coupled to one of a feedback path configured to provide the feedback clock signal and a forward path configured to receive the input clock signal; and enabling selected capacitors to generate the variable delay.
Claim 82
Independent Claim
128 words
A method, comprising: receiving an input clock signal; delaying the input clock signal by a time interval to generate an output clock signal; receiving a feedback clock signal based on the output signal; detecting a phase alignment error between the input clock signal and the feedback clock signal; controlling the lime interval to a synchronize the input clock signal with the feedback clock signal; and introducing a variable delay in one of the input clock signal and the feedback clock signal responsive to a test mode enable signal by: providing a plurality of capacitors coupled to one of a feedback path configured to provide the feedback clock signal and a forward path configured to receive the input clock signal; and enabling selected capacitors to generate the variable delay.
Claim 83
Dependent Claim
25 words
The method of claim 72 , wherein enabling the selected capacitors further comprises enabling the selected capacitors using a counter having a plurality of stages.
Claim 84
Dependent Claim
37 words
The method of claim 73 , wherein providing the capacitors further comprises providing a plurality of weighted capacitors, each weighted capacitor having a weighted capacitance based on the stage of the counter by which it is enabled.
Claim 85
Dependent Claim
35 words
The method of claim 73 , wherein providing the capacitors further comprises providing banks of capacitors, each bank having an associated weighted capacitance based on the stage of the counter by which it is enabled.
Claim 86
Independent Claim
94 words
A device, comprising: a delay locked loop including: a forward path for receiving an input clock signal and a feedback path for synchronizing the input clock signal with a feedback clock signal; and a noise filter, wherein the noise filter is configured to be disabled responsive to the assertion of a test mode enable signal; and a dither circuit coupled to one of the forward path and the feedback path and being configured to introduce a delay to simulate an environmental variation in the delay locked loop responsive to the test mode enable signal.
Claim 87
Independent Claim
94 words
A device, comprising: a delay locked loop including: a forward path for receiving an input clock signal and a feedback path for synchronizing the input clock signal with a feedback clock signal; and a noise filter, wherein the noise filter is configured to be disabled responsive to the assertion of a test mode enable signal; and a dither circuit coupled to one of the forward path and the feedback path and being configured to introduce a delay to simulate an environmental variation in the delay locked loop responsive to the test mode enable signal.
Claim 88
Independent Claim
75 words
A method, comprising: providing a delay locked loop for synchronizing an input clock signal having a period with a feedback clock signal; receiving a test mode enable signal; and introducing a variable delay in one of the input clock signal and the feedback clock signal to simulate an environmental variation in the delay locked loop responsive to the test mode enable signal, the variable delay being less than one period of the input clock signal.
Claim 89
Independent Claim
75 words
A method, comprising: providing a delay locked loop for synchronizing an input clock signal having a period with a feedback clock signal; receiving a test mode enable signal; and introducing a variable delay in one of the input clock signal and the feedback clock signal to simulate an environmental variation in the delay locked loop responsive to the test mode enable signal, the variable delay being less than one period of the input clock signal.
Claim 90
Dependent Claim
18 words
The method of claim 77 , wherein introducing the variable delay further comprises introducing a periodic variable delay.
Claim 91
Dependent Claim
23 words
The method of claim 78 , wherein introducing the periodic variable delay further comprises introducing the periodic variable delay having a triangular waveform.
Claim 92
Dependent Claim
23 words
The method of claim 78 , wherein introducing the periodic variable delay further comprises introducing the periodic variable delay having a sawtooth waveform.
Claim 93
Dependent Claim
32 words
The method of claim 77 wherein introducing the delay further comprises: providing a plurality of delay elements coupled to the delay locked loop; and enabling selected delay elements to generate the delay.
Claim 94
Dependent Claim
23 words
The method of claim 81 , wherein enabling the selected delay elements further comprises enabling selected capacitors coupled to the delay locked loop.
Claim 95
Dependent Claim
25 words
The method of claim 82 , wherein enabling the selected capacitors further comprises enabling the selected capacitors using a counter having a plurality of stages.
Claim 96
Dependent Claim
37 words
The method of claim 83 , wherein providing the capacitors further comprises providing a plurality of weighted capacitors each weighted capacitor having a weighted capacitance based on the stage of the counter by which it is enabled.
Claim 97
Dependent Claim
35 words
The method of claim 83 , wherein providing the capacitors further comprises providing banks of capacitors, each bank having an associated weighted capacitance based on the stage of the counter by which it is enabled.
Claim 98
Dependent Claim
34 words
The method of claim 77 , wherein the delay locked loop includes a noise filter, and the method further comprises disabling the noise filter responsive to the assertion of the test mode enable signal.
Claim 99
Independent Claim
82 words
A method, comprising: providing a delay locked loop for synchronizing an input clock signal with a feedback clock signal, wherein the delay locked loop includes a noise filter; receiving a test mode enable signal; introducing a variable delay in one of the input clock signal end the feedback clock signal to simulate an environmental variation in the delay looked loop responsive to the test mode enable signal; and disabling the noise filter responsive to the assertion of the test mode enable signal.
Claim 100
Independent Claim
82 words
A method, comprising: providing a delay locked loop for synchronizing an input clock signal with a feedback clock signal, wherein the delay locked loop includes a noise filter; receiving a test mode enable signal; introducing a variable delay in one of the input clock signal end the feedback clock signal to simulate an environmental variation in the delay looked loop responsive to the test mode enable signal; and disabling the noise filter responsive to the assertion of the test mode enable signal.
Claim 101
Independent Claim
72 words
A method, comprising: providing a delay locked loop for synchronizing an input clock signal with a feedback clock signal; receiving a rest mode enable signal; introducing a delay in one of the input clock signal and the feedback clock signal to simulate an environmental variation in the delay locked loop responsive to the test mode enable signal; and measuring a skew between transitions of a data signal and the input clock signal.
Claim 102
Independent Claim
72 words
A method, comprising: providing a delay locked loop for synchronizing an input clock signal with a feedback clock signal; receiving a rest mode enable signal; introducing a delay in one of the input clock signal and the feedback clock signal to simulate an environmental variation in the delay locked loop responsive to the test mode enable signal; and measuring a skew between transitions of a data signal and the input clock signal.
Claim 103
Dependent Claim
19 words
The method of claim 88 , further comprising determining an access time parameter, tAC, based on the measured skew.
Claim 104
Dependent Claim
21 words
The method of claim 89 , further comprising determining a minimum tAC and a maximum tAC based on the measured skew.
Claim 105
Dependent Claim
23 words
The method of claim 89 , further comprising identifying a fault condition responsive to the determined tAC being greater that a design threshold.
Claim 106
Dependent Claim
21 words
The method of claim 88 , wherein introducing the delay further comprises introducing a variable delay in the feedback clock signal.
Claim 107
Dependent Claim
170 words
A delay locked loop, comprising: a forward path including a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal; a feedback path configured to provide a feedback clock signal based on the output clock signal; a phase detector configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; a dither circuit coupled to the delay line configured to introduce a delay responsive to an assertion of a test mode enable signal; and a noise filter coupled to the phase detector and being configured to reduce noise in the shift signal, wherein the noise filter is configured to be disabled responsive to the assertion of the test mode enable signal.
Claim 108
Dependent Claim
170 words
A delay locked loop, comprising: a forward path including a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal; a feedback path configured to provide a feedback clock signal based on the output clock signal; a phase detector configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; a dither circuit coupled to the delay line configured to introduce a delay responsive to an assertion of a test mode enable signal; and a noise filter coupled to the phase detector and being configured to reduce noise in the shift signal, wherein the noise filter is configured to be disabled responsive to the assertion of the test mode enable signal.
Claim 109
Independent Claim
177 words
A system, comprising: a first digital device configured to provide a first clock signal and a test mode enable signal; and a second digital device configured to receive the first clock signal and generate a second clock signal, the second digital device including: a forward path including a delay line configured to receive the first clock signal and delay the first clock signal by a time interval to generate the second clock signal; a feedback path configured to provide a feedback clock signal based on the second clock signal; a phase detector configured to compare the first clock signal and the feedback clock signal and generate a shift signal if the second clock signal is not in phase with the first clock signal; logic coupled to the delay line and being coupled to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to the delay line and the forward path and being configured to introduce a delay responsive to an assertion of a test mode enable signal.
Claim 110
Independent Claim
177 words
A system, comprising: a first digital device configured to provide a first clock signal and a test mode enable signal; and a second digital device configured to receive the first clock signal and generate a second clock signal, the second digital device including: a forward path including a delay line configured to receive the first clock signal and delay the first clock signal by a time interval to generate the second clock signal; a feedback path configured to provide a feedback clock signal based on the second clock signal; a phase detector configured to compare the first clock signal and the feedback clock signal and generate a shift signal if the second clock signal is not in phase with the first clock signal; logic coupled to the delay line and being coupled to receive the shift signal and control the time interval based on the shift signal; and a dither circuit coupled to the delay line and the forward path and being configured to introduce a delay responsive to an assertion of a test mode enable signal.
Claim 111
Independent Claim
210 words
A system, comprising: a first digital device configured to provide a first clock signal and a test mode enable signal; and a second digital device configured to receive the first clock signal and generate a second clock signal, the second digital device including: a forward path including a delay line configured to receive the first clock signal and delay the first clock signal by a time interval to generate the second clock signal; a feedback path configured to provide a feedback clock signal based on the second clock signal; a phase detector configured to compare the first clock signal and the feedback clock signal and generate a shift signal if the second clock signal is not in phase with the first clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; a dither circuit coupled to the delay line and configured to introduce a variable delay responsive to an assertion of a test mode enable signal; and a noise filter coupled to the phase detector and being configured to reduce noise in the shift signal, wherein the noise filter is configured to be disabled responsive to the assertion of the test mode enable signal.
Claim 112
Independent Claim
210 words
A system, comprising: a first digital device configured to provide a first clock signal and a test mode enable signal; and a second digital device configured to receive the first clock signal and generate a second clock signal, the second digital device including: a forward path including a delay line configured to receive the first clock signal and delay the first clock signal by a time interval to generate the second clock signal; a feedback path configured to provide a feedback clock signal based on the second clock signal; a phase detector configured to compare the first clock signal and the feedback clock signal and generate a shift signal if the second clock signal is not in phase with the first clock signal; logic coupled to the delay line and being configured to receive the shift signal and control the time interval based on the shift signal; a dither circuit coupled to the delay line and configured to introduce a variable delay responsive to an assertion of a test mode enable signal; and a noise filter coupled to the phase detector and being configured to reduce noise in the shift signal, wherein the noise filter is configured to be disabled responsive to the assertion of the test mode enable signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-08-10 | 2008-02-09 | 2008-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-08-10 | 2012-02-09 | 2012-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-08-10 | 2016-02-09 | 2016-08-10 | $7700.00 | Window Closed / Lapsed |