US6476594B1
Expired / Lapsed
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Method and apparatus for testing high frequency delay locked loops
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2001-05-31
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Granted: 2002-11-05
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Expires: 2021-05-31
Abstract
Abstract A delay-locked loop circuit is provided which includes a delay-locked loop, a delay element and a multiplexer. The delay-locked loop has a reference clock input, a feedback clock input and a clock output. The delay element has a delay input which is coupled to the clock output and a delay output. The multiplexer has a first multiplexer input which is coupled to the clock output, a second multiplexer input which is coupled to the delay output and a multiplexer output which is coupled to the feedback input.
Inventors
- 👤 Roger L. Roisen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:52
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
68 words
A delay-locked loop circuit comprising: a delay-locked loop having a reference clock input, a feedback clock input and a clock output; a delay element having a delay input coupled to the clock output and a delay output; and a multiplexer having a first multiplexer input coupled to the clock output, a second multiplexer input coupled to the delay output and a multiplexer output coupled to the feedback input.
Claim 2
Dependent Claim
68 words
A delay-locked loop circuit comprising: a delay-locked loop having a reference clock input, a feedback clock input and a clock output; a delay element having a delay input coupled to the clock output and a delay output; and a multiplexer having a first multiplexer input coupled to the clock output, a second multiplexer input coupled to the delay output and a multiplexer output coupled to the feedback input.
Claim 3
Dependent Claim
28 words
The delay-locked loop of claim 1 wherein the delay element comprises a plurality of semiconductor cells connected together in series between the delay input and the delay output.
Claim 4
Dependent Claim
46 words
The delay-locked loop circuit of claim 1 wherein the multiplexer further comprises: a normal operating state in which the multiplexer couples the first multiplexer input to the multiplexer output; and a test state in which the multiplexer couples the second multiplexer input to the multiplexer output.
Claim 5
Dependent Claim
47 words
The delay-locked loop circuit of claim 3 wherein the delay locked loop comprises a first target frequency when the multiplexer is in the normal operating state and a second target frequency, which is smaller than the first target frequency, when the multiplexer is in the test state.
Claim 6
Independent Claim
118 words
A method of testing a delay-locked loop that is embedded within an integrated circuit, the method comprising: (a) applying a test clock to a reference clock input of the delay-locked loop, wherein the test clock signal has a frequency that is outside a normal locking range of the delay-locked loop; (b) lowering the normal locking range of the delay-locked loop to a test locking range, wherein the frequency of the test clock signal is within the test locking range; and (c) detecting a representation of an output clock signal generated by the delay-locked loop on a clock output of the delay-locked loop in response to the test clock signal when the delay-locked loop has the test locking range.
Claim 7
Independent Claim
118 words
A method of testing a delay-locked loop that is embedded within an integrated circuit, the method comprising: (a) applying a test clock to a reference clock input of the delay-locked loop, wherein the test clock signal has a frequency that is outside a normal locking range of the delay-locked loop; (b) lowering the normal locking range of the delay-locked loop to a test locking range, wherein the frequency of the test clock signal is within the test locking range; and (c) detecting a representation of an output clock signal generated by the delay-locked loop on a clock output of the delay-locked loop in response to the test clock signal when the delay-locked loop has the test locking range.
Claim 8
Dependent Claim
40 words
The method of claim 5 wherein step (c) comprises: (c)(1) dividing a frequency of the output clock signal from a first frequency to a second, lower frequency and detecting a representation of the output clock signal at the second frequency.
Claim 9
Dependent Claim
39 words
The method of claim 5 wherein step (a) comprises generating the test clock signal with a tester that is external to the integrated circuit and step (d) comprises detecting the representation of the output clock signal with the tester.
Claim 10
Dependent Claim
39 words
The method of claim 5 wherein step (b) comprises: (b)(1) selectively inserting a delay element within a feedback path in the delay-locked loop that is coupled between the clock output and a feedback clock input of the delay-locked loop.
Claim 11
Dependent Claim
62 words
The method of claim 8 wherein: the test clock signal has a cycle time; the delay locked loop has a target cycle time when the delay-locked loop has the normal locking; and the delay element has a propagation delay that is approximately equal to the cycle time of the test clock signal minus the target cycle time of the delay locked loop.
Claim 12
Dependent Claim
95 words
The method of claim 8 wherein step (b)(1) comprises: (b)(1)(i) coupling the clock output to a first input of a multiplexer; (b)(1)(ii) coupling the clock output to a second input of a multiplexer, through the delay element; (b)(1)(iii) coupling an output of the multiplexer to the feedback clock input of the delay-locked loop; and (b)(1)(iv) switching the multiplexer from a normal operating state, in which the first multiplexer input is coupled to the output of the multiplexer, to a test state, in which the second multiplexer input is coupled to the output of the multiplexer.
Claim 13
Dependent Claim
74 words
An integrated circuit comprising: an embedded delay-locked loop having a reference clock input, a feedback clock input, a test control input, a clock output and a feedback path from the clock output to the feedback clock input; and means for selectively changing a locking range of the delay-locked loop from a first frequency range to a second, slower frequency range as a function of a test control signal applied to the test control input.
Claim 14
Dependent Claim
74 words
An integrated circuit comprising: an embedded delay-locked loop having a reference clock input, a feedback clock input, a test control input, a clock output and a feedback path from the clock output to the feedback clock input; and means for selectively changing a locking range of the delay-locked loop from a first frequency range to a second, slower frequency range as a function of a test control signal applied to the test control input.
Claim 15
Dependent Claim
35 words
The integrated circuit of claim 11 wherein the means for selectively changing the locking range comprises: means for selectively inserting a delay element into the feedback path as a function of the test control signal.
Claim 16
Dependent Claim
51 words
The integrated circuit of claim 12 wherein the means for selectively inserting comprises: a multiplexer having a first multiplexer input which is coupled to the clock output, a second multiplexer input which is coupled to the clock output through the delay element, and a multiplexer output coupled to the feedback input.
Claim 17
Dependent Claim
24 words
The integrated circuit of claim 12 wherein the delay element comprises a plurality of semiconductor buffer cells coupled together in series with one another.
References Cited (Backward Citations)
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