US6085345A
Expired / Lapsed
US
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Timing control for input/output testability
Assignee: Intel Corp
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Filing: 1997-12-24
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Granted: 2000-07-04
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Expires: 2017-12-24
Abstract
Abstract Circuitry added to chips that use source synchronous techniques reduces difficulties associated with testing the chips. The circuitry increases the ability to use source synchronous techniques for data transmission. The circuitry is implemented in a delayed-lock loop (DLL) in either a transmitter (driver) or a receiver. The DLL measures the phase difference between a strobe signal and a delayed strobe signal. The DLL can be externally controlled by a source selectable input which allows the delay of the delayed strobe signal to be varied to test T setup and T hold in the receiver without varying the timings of the strobe signal and the data signals supplied to the chips. A timing measurement circuit having the strobe signal, the delayed strobe signal, and reference signals as inputs may be used to calibrate the phase difference between the strobe signal and delayed strobe signal.
Inventors
- 👤 Gregory F. Taylor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:12
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3016; H; H03; H03K; H03K5/00; H03K5/22; H03K5/26; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
109 words
A circuit for measuring phase difference between first and second binary signals comprising: logic having a first logic input coupled to the first binary signal, a second logic input coupled to the second binary signal, and a logic output for producing a binary output signal whose duty cycle varies according to the phase difference between the first and second binary signals; a filter coupled to the logic output to filter the binary output signal; and signal conversion logic coupled to an output of the filter to produce a digital indicator of a value of the duty cycle; wherein the digital indicator is a digital number representing the phase difference.
Claim 2
Dependent Claim
109 words
A circuit for measuring phase difference between first and second binary signals comprising: logic having a first logic input coupled to the first binary signal, a second logic input coupled to the second binary signal, and a logic output for producing a binary output signal whose duty cycle varies according to the phase difference between the first and second binary signals; a filter coupled to the logic output to filter the binary output signal; and signal conversion logic coupled to an output of the filter to produce a digital indicator of a value of the duty cycle; wherein the digital indicator is a digital number representing the phase difference.
Claim 3
Dependent Claim
12 words
The circuit of claim 1, wherein the logic comprises an exclusive-OR gate.
Claim 4
Dependent Claim
13 words
The circuit of claim 1, wherein the filter comprises a low pass filter.
Claim 5
Dependent Claim
14 words
The circuit of claim 1, wherein the signal conversion logic comprises an analog-to-digital converter.
Claim 6
Dependent Claim
77 words
The circuit of claim 1, further comprising: a first multiplexer having: a first multiplexer input coupled to a first strobe signal; a second multiplexer input coupled to a first reference signal; and a first multiplexer output coupled to the first logic input; a second multiplexer having: a third multiplexer input coupled to a second strobe signal; a fourth multiplexer input coupled to a second reference signal; and a second multiplexer output coupled to the second logic input.
Claim 7
Dependent Claim
18 words
The circuit of claim 5, wherein the first and second reference signals are for calibration of the circuit.
Claim 8
Dependent Claim
27 words
The circuit of claim 6, wherein a signal at the filter output includes a ripple component and successive digital indicators indicate an amount of the ripple component.
Claim 9
Dependent Claim
19 words
The circuit of claim 1, wherein the second binary signal comprises a delayed version of the first binary signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-04 | 2004-01-03 | 2004-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-04 | 2008-01-03 | 2008-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-04 | 2012-01-03 | 2012-07-04 | $7700.00 | Window Closed / Lapsed |