US6414903B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for crossing clock domain boundaries
Assignee: Round Rock Research LLC
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Filing: 2001-06-21
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Granted: 2002-07-02
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Expires: 2021-06-21
Abstract
Abstract A method and apparatus that expands the data envelope of captured data to a predetermined number of clocks cycles. The predetermined number of clock cycles is large enough to ensure that an internally generated master clock edge remains within the data envelope over the entire operating range. This way, captured data remains valid and can be properly transferred to the master clock domain from a capture clock domain despite temperature and voltage variations that may effect the timing of the memory device.
Inventors
- 👤 Brent Keeth
- 👤 Brian Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:56
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/22; G11C7/222; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C7/10; G11C7/1072; G11C7/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
103 words
A memory device comprising: data capture circuitry for capturing and latching a plurality of input data signals responsive to a first clock signal, said data capture circuit outputting a plurality of captured data signals; a first circuit for generating a plurality of synchronization signals responsive to the first clock signal, said synchronization signals simulating a timing of some of the plurality of input data signals; and a second circuit responsive to a second clock signal, said second circuit receiving said plurality of synchronization signals and re-timing said captured data signals to be aligned with said second clock signal based on said synchronization signals.
Claim 2
Dependent Claim
103 words
A memory device comprising: data capture circuitry for capturing and latching a plurality of input data signals responsive to a first clock signal, said data capture circuit outputting a plurality of captured data signals; a first circuit for generating a plurality of synchronization signals responsive to the first clock signal, said synchronization signals simulating a timing of some of the plurality of input data signals; and a second circuit responsive to a second clock signal, said second circuit receiving said plurality of synchronization signals and re-timing said captured data signals to be aligned with said second clock signal based on said synchronization signals.
Claim 3
Dependent Claim
61 words
The memory device of claim 1 , wherein said first circuit is controllable by first and second clock edge selection signals such that some of said plurality of synchronization signals are aligned with a first transition of the first clock signal and the remaining of said plurality of synchronization signals are aligned with a second transition of the first clock signal.
Claim 4
Dependent Claim
80 words
The memory device of claim 1 , wherein said data capture circuit comprises: a plurality of first latch circuits, each first latch circuit having a first input for receiving the first clock signal and a second input for receiving respective input data signals, each first latch circuit being controllable to latch its respective input data signals such that the latched input data signals have a data envelope corresponding to N number of cycles of the first clock signal, where N>1.
Claim 5
Dependent Claim
11 words
The memory device of claim 3 , wherein N is three.
Claim 6
Dependent Claim
111 words
The memory device of claim 1 , wherein said second circuit comprises: a reset circuit for generating a synchronization request signal, said reset circuit coupled to said synchronization signals and the second clock signal, said reset circuit outputting said synchronization request signal based on a timing of said synchronization signals with respect to the second clock signal; a selection circuit for generating at least one selection signal responsive to said synchronization request signal; and a data generator receiving said at least one selection signal and said captured data signals and re-timing said captured data signals to be aligned with said second clock signal responsive to said at least one selection signal.
Claim 7
Dependent Claim
116 words
A processor system comprising: a processor; and a memory device connected to said processor, said memory device comprising: data capture circuitry for capturing and latching a plurality of input data signals responsive to a first clock signal, said data capture circuit outputting a plurality of captured data signals; a first circuit for generating a plurality of synchronization signals responsive to the first clock signal, said synchronization signals simulating a timing of some of the plurality of input data signals; a second circuit responsive to a second clock signal, said second circuit receiving said plurality of synchronization signals and re-timing said captured data signals to be aligned with said second clock signal based on said synchronization signals.
Claim 8
Dependent Claim
116 words
A processor system comprising: a processor; and a memory device connected to said processor, said memory device comprising: data capture circuitry for capturing and latching a plurality of input data signals responsive to a first clock signal, said data capture circuit outputting a plurality of captured data signals; a first circuit for generating a plurality of synchronization signals responsive to the first clock signal, said synchronization signals simulating a timing of some of the plurality of input data signals; a second circuit responsive to a second clock signal, said second circuit receiving said plurality of synchronization signals and re-timing said captured data signals to be aligned with said second clock signal based on said synchronization signals.
Claim 9
Dependent Claim
61 words
The system device of claim 6 , wherein said first circuit is controllable by first and second clock edge selection signals such that some of said plurality of synchronization signals are aligned with a first transition of the first clock signal and the remaining of said plurality of synchronization signals are aligned with a second transition of the first clock signal.
Claim 10
Dependent Claim
79 words
The system of claim 6 , wherein said data capture circuit comprises: a plurality of first latch circuits, each first latch circuit having a first input for receiving the first clock signal and a second input for receiving respective input data signals, each first latch circuit being controllable to latch its respective input data signals such that the latched input data signals have a data envelope corresponding to N number of cycles of the first clock signal, where N>1.
Claim 11
Dependent Claim
10 words
The system of claim 8 , wherein N is three.
Claim 12
Dependent Claim
111 words
The system of claim 6 , wherein said second circuit comprises: a reset circuit for generating a synchronization request signal, said reset circuit coupled to said synchronization signals and the second clock signal, said reset circuit outputting said synchronization request signal based on a timing of said synchronization signals with respect to the second clock signal; a selection circuit for generating at least one selection signal responsive to said synchronization request signal; and a data generator receiving said at least one selection signal and said captured input signals and re-timing said captured input data signals to be aligned with said second clock signal responsive to said at least one selection signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-07-01 | 2005-12-31 | 2006-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-01 | 2009-12-31 | 2010-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-01 | 2013-12-31 | 2014-07-02 | $7700.00 | Window Closed / Lapsed |