US6768663B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device array having dense memory cell array and hierarchical bit line scheme
Assignee: Texas Instruments Inc
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Filing: 2003-05-02
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Granted: 2004-07-27
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Expires: 2023-05-02
Abstract
Abstract A semiconductor device architecture ( 200 ) is disclosed. Like unit circuits ( 202 ), arranged in rows and columns, are coupled to lower conductive segments ( 204 a- 204 h ). The lower conductive segments ( 204 a- 204 h ) are arranged in an “open” configuration, allowing adjacent unit circuits ( 202 ) be accessed simultaneously. The lower conductive segments ( 204 a- 204 h ) are coupled to higher conductive segments ( 208 a- 208 t ) by reconnector circuits ( 210 a and 210 b ). The higher conductive segments ( 208 a- 208 t ) are arranged into folded pairs ( 208 a/ 208 d, 208 b/ 208 e and 208 c/ 208 f ) between differential-type amplifiers ( 212 a and 212 b ). The reconnector circuits ( 210 a and 210 b ) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits ( 210 a and 210 b ) couple adjacent folded higher conductive segment pairs to one another. In a switch configuration, the reconnector circuits ( 210 a and 210 b ) couple a matching lower conductive segment ( 204 a- 204 h ) to each higher conductive segment of the adjacent higher conductive segment pairs.
Inventors
- 👤 Yoshihiro Ogata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:14
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; H; H10; H10B; H10B12/00; H10B12/30; H10B12/48; H10B12/50
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
271 words
A high-density semiconductor memory device, comprising: a plurality of lower-order conductive segments arranged into lower-order connected groups, each lower-order connected group including a first lower-order conductive segment associated with a first sense amplifier circuit, a second lower-order conductive segment associated with the first sense amplifier circuit, the second lower-order conductive segment being situated adjacent to the first lower-order conductive segment in a first direction, a third lower-order conductive segment associated with a second sense amplifier circuit, the third lower-order conductive segment being situated adjacent to the first lower-order conductive segment in a second direction that is generally perpendicular to the first direction, a fourth lower-order conductive segment associated with the second sense amplifier circuit, the fourth lower-order conductive segment being situated adjacent to the second lower-order conductive segment in the second direction, a plurality of higher-order conductive segments coupled to sense amplifiers in pairs, the higher-order conductive segments including a first folded pair that includes a first higher-order conductive segment and a second higher-order conductive segment, and a second folded pair that includes a third higher-order conductive segment and a fourth higher-order conductive segment; a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration coupling the first higher-order conductive segment to the first lower-order conductive segment, coupling the second higher-order conductive segment to the second lower-order conductive segment, coupling the third higher-order conductive segment to the third lower-order conductive segment, and coupling the fourth higher-order conductive segment to the fourth lower-order conductive segment, and the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments.
Claim 2
Dependent Claim
271 words
A high-density semiconductor memory device, comprising: a plurality of lower-order conductive segments arranged into lower-order connected groups, each lower-order connected group including a first lower-order conductive segment associated with a first sense amplifier circuit, a second lower-order conductive segment associated with the first sense amplifier circuit, the second lower-order conductive segment being situated adjacent to the first lower-order conductive segment in a first direction, a third lower-order conductive segment associated with a second sense amplifier circuit, the third lower-order conductive segment being situated adjacent to the first lower-order conductive segment in a second direction that is generally perpendicular to the first direction, a fourth lower-order conductive segment associated with the second sense amplifier circuit, the fourth lower-order conductive segment being situated adjacent to the second lower-order conductive segment in the second direction, a plurality of higher-order conductive segments coupled to sense amplifiers in pairs, the higher-order conductive segments including a first folded pair that includes a first higher-order conductive segment and a second higher-order conductive segment, and a second folded pair that includes a third higher-order conductive segment and a fourth higher-order conductive segment; a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration coupling the first higher-order conductive segment to the first lower-order conductive segment, coupling the second higher-order conductive segment to the second lower-order conductive segment, coupling the third higher-order conductive segment to the third lower-order conductive segment, and coupling the fourth higher-order conductive segment to the fourth lower-order conductive segment, and the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments.
Claim 3
Dependent Claim
41 words
The high-density semiconductor memory device of claim 1 , wherein: the reconnector circuit reconnect mode further couples the first higher-order conductive segment to the third higher-order conductive segment, and couples the second higher-order conductive segment to the fourth higher-order conductive segment.
Claim 4
Dependent Claim
41 words
The high-density semiconductor memory device of claim 1 , wherein: the reconnector circuit switch mode further couples the first higher-order conductive segment to the fourth higher-order conductive segment, and couples the second higher-order conductive segment to the third higher-order conductive segment.
Claim 5
Dependent Claim
37 words
The high-density semiconductor memory device of claim 1 , wherein: the higher-order conductive segments extend in the first direction, parallel to one another; and the lower-order conductive segments extend in the first direction parallel to one another.
Claim 6
Dependent Claim
37 words
The high-density semiconductor memory device of claim 1 , wherein: the higher-order conductive segments extend in the first direction, parallel to one another; and the lower-order conductive segments extend at angles with respect to the first direction.
Claim 7
Dependent Claim
103 words
The high-density semiconductor memory device of claim 1 , wherein: the reconnector circuit includes a first switch insulated gate field effect transistors (IGFET) having a source-drain path coupled between the first higher-order conductive segment and the first lower-order conductive segment, a second switch IGFET having a source-drain path coupled between the second higher-order conductive segment and the second lower-order conductive segment, a third switch IGFET having a source-drain path coupled between the third higher-order conductive segment and the third lower-order conductive segment, and a fourth IGFET having a source-drain path coupled between the fourth higher-order conductive segment and the fourth lower-order conductive segment.
Claim 8
Dependent Claim
57 words
The high-density semiconductor memory device of claim 1 , wherein: the reconnector circuit includes a first reconnector IGFET having a source-drain path coupled between the first higher-order conductive segment and the third higher-order conductive segment, and a second reconnector IGFET having a source-drain path coupled between the second higher-order conductive segment and the fourth higher-order conductive segment.
Claim 9
Dependent Claim
94 words
A high-density semiconductor memory device, comprising: a plurality of lower-order conductive segments arranged into lower-order connected groups; a plurality of higher-order conductive segments coupled to sense amplifiers in pairs; a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration coupling selected higher-order conductive segments with selected lower-order conductive segments; and the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments; the reconnector circuit reconnect configuration further coupling selected higher-order conductive segments to other selected higher-order conductive segments.
Claim 10
Dependent Claim
94 words
A high-density semiconductor memory device, comprising: a plurality of lower-order conductive segments arranged into lower-order connected groups; a plurality of higher-order conductive segments coupled to sense amplifiers in pairs; a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration coupling selected higher-order conductive segments with selected lower-order conductive segments; and the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments; the reconnector circuit reconnect configuration further coupling selected higher-order conductive segments to other selected higher-order conductive segments.
Claim 11
Dependent Claim
27 words
The high-density semiconductor memory device of claim 8 , wherein the reconnector circuit switch configuration further couples selected higher-order conductive segments to other selected higher-order conductive segments.
Claim 12
Dependent Claim
37 words
The high-density semiconductor memory device of claim 8 , wherein: the higher-order conductive segments extend in a first direction, parallel to one another; and the lower-order conductive segments extend in the first direction parallel to one another.
Claim 13
Dependent Claim
105 words
A high-density semiconductor memory device, comprising: a plurality of lower-order conductive segments arranged into lower-order connected groups; a plurality of higher-order conductive segments coupled to sense amplifiers in pairs; a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration coupling selected higher-order conductive segments with selected lower-order conductive segments; and the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments; wherein: the higher-order conductive segments extend in a first direction, parallel to one another; and the lower-order conductive segments extend at angles with respect to the first direction.
Claim 14
Dependent Claim
105 words
A high-density semiconductor memory device, comprising: a plurality of lower-order conductive segments arranged into lower-order connected groups; a plurality of higher-order conductive segments coupled to sense amplifiers in pairs; a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration coupling selected higher-order conductive segments with selected lower-order conductive segments; and the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments; wherein: the higher-order conductive segments extend in a first direction, parallel to one another; and the lower-order conductive segments extend at angles with respect to the first direction.
Claim 15
Dependent Claim
171 words
A high-density semiconductor memory device, comprising: a plurality of lower-order conductive segments arranged into lower-order connected groups; a plurality of higher-order conductive segments coupled to sense amplifiers in pairs; a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration coupling selected higher-order conductive segments with selected lower-order conductive segments; and the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments; wherein: the reconnector circuit includes a first switch insulated gate field effect transistor (IGFET) having a source-drain path coupled between a first higher-order conductive segment and a first lower-order conductive segment, a second switch IGFET having a source-drain path coupled between a second higher-order conductive segment and a second lower-order conductive segment, a third switch IGFET having a source-drain path coupled between a third higher-order conductive segment and a third lower-order conductive segment, and a fourth IGFET having a source-drain path coupled between a fourth higher-order conductive segment and a fourth lower-order conductive segment.
Claim 16
Dependent Claim
171 words
A high-density semiconductor memory device, comprising: a plurality of lower-order conductive segments arranged into lower-order connected groups; a plurality of higher-order conductive segments coupled to sense amplifiers in pairs; a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration coupling selected higher-order conductive segments with selected lower-order conductive segments; and the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments; wherein: the reconnector circuit includes a first switch insulated gate field effect transistor (IGFET) having a source-drain path coupled between a first higher-order conductive segment and a first lower-order conductive segment, a second switch IGFET having a source-drain path coupled between a second higher-order conductive segment and a second lower-order conductive segment, a third switch IGFET having a source-drain path coupled between a third higher-order conductive segment and a third lower-order conductive segment, and a fourth IGFET having a source-drain path coupled between a fourth higher-order conductive segment and a fourth lower-order conductive segment.
Claim 17
Dependent Claim
112 words
A high-density semiconductor memory device, comprising: a plurality of lower-order conductive segments arranged into lower-order connected groups; a plurality of higher-order conductive segments coupled to sense amplifiers in pairs; a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration coupling selected higher-order conductive segments with selected lower-order conductive segments; and the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments, wherein: the reconnector circuit includes a first reconnector IGFET having a source-drain path coupled between two higher-order conductive segments, and a second reconnector IGFET having a source-drain path coupled between two other higher-order conductive segments.
Claim 18
Dependent Claim
112 words
A high-density semiconductor memory device, comprising: a plurality of lower-order conductive segments arranged into lower-order connected groups; a plurality of higher-order conductive segments coupled to sense amplifiers in pairs; a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration coupling selected higher-order conductive segments with selected lower-order conductive segments; and the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments, wherein: the reconnector circuit includes a first reconnector IGFET having a source-drain path coupled between two higher-order conductive segments, and a second reconnector IGFET having a source-drain path coupled between two other higher-order conductive segments.
References Cited (Backward Citations)
US4888732A
Cited
JPH0198189A
Cited
US5034920A
Cited
US5440521A
Cited
US5555519A
Cited
USRE36993E
Cited
US5610871A
Cited
JP2002016147A
Cited
US5999480A
Cited
US20020000837A1
Cited
US5864496A
Cited
US5966315A
Cited
US6069815A
Cited
US6125076A
Cited
US6333866B1
Cited
US6580629B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2007-07-27 | 2008-01-26 | 2008-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-07-27 | 2012-01-26 | 2012-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-07-27 | 2016-01-26 | 2016-07-27 | $7700.00 | Window Closed / Lapsed |