US5864496A — High density semiconductor memory having diagonal…

Claim 1

Independent Claim 129 words

A semiconductor memory, comprising: a memory cell array of memory cells arranged in rows and columns; a plurality of diagonal bit lines arranged in a pattern that changes horizontal direction along said memory cell array to facilitate access to said memory cells; a plurality of dual word lines non-orthogonal to the bit lines, wherein a dual word line includes a master word line at a first layer and a plurality of local word lines at a second layer, the local word lines being connected to the master word line of a common row via a plurality of spaced electrical connections, each local word line being connected to plural memory cells; wherein said electrical connections run in substantially said pattern having changes in horizontal direction along the memory cell array.

Claim 2

Dependent Claim 129 words

A semiconductor memory, comprising: a memory cell array of memory cells arranged in rows and columns; a plurality of diagonal bit lines arranged in a pattern that changes horizontal direction along said memory cell array to facilitate access to said memory cells; a plurality of dual word lines non-orthogonal to the bit lines, wherein a dual word line includes a master word line at a first layer and a plurality of local word lines at a second layer, the local word lines being connected to the master word line of a common row via a plurality of spaced electrical connections, each local word line being connected to plural memory cells; wherein said electrical connections run in substantially said pattern having changes in horizontal direction along the memory cell array.

Claim 3

Dependent Claim 19 words

The semiconductor memory of claim 1 wherein said electrical connections are electrical contacts between said first and second layers.

Claim 4

Dependent Claim 14 words

The semiconductor memory of claim 1 wherein said bit lines are folded bit lines.

Claim 5

Dependent Claim 35 words

The semiconductor memory of claim 3, wherein a vertical twist in the folded bit lines occurs at each region of the semiconductor memory where a change in horizontal direction of the bit line pattern occurs.

Claim 6

Dependent Claim 18 words

The semiconductor memory of claim 1 wherein said bit lines are arranged in an open bit line configuration.

Claim 7

Dependent Claim 25 words

The semiconductor memory of claim 1, wherein said memory cells are substantially 6F 2 cells where F represents the minimum feature size of memory elements.

Claim 8

Dependent Claim 19 words

The semiconductor memory of claim 1 wherein said electrical connections are arranged in an interleaved configuration in alternating rows.

Claim 9

Dependent Claim 33 words

The semiconductor memory of claim 1 wherein distances between adjacent electrical connections of a common row vary along any given row to substantially equalize delay times in accessing memory cells along the row.

Claim 10

Dependent Claim 18 words

The semiconductor memory of claim 1 wherein said pattern having changes in horizontal direction is a zigzag-type pattern.

Claim 11

Dependent Claim 15 words

The semiconductor memory of claim 1 wherein said memory comprises a dynamic random access memory.

Claim 12

Dependent Claim 209 words

A semiconductor memory, comprising: a memory cell array having a major surface in a first plane; a plurality of bit line pairs, wherein a bit line comprises a true bit line coupled to a plurality of true memory cells and an associated complementary bit line coupled to a plurality of complementary memory cells, the true bit line being periodically twisted with the associated complementary bit line such that the true bit line alternately overlies and underlies the complementary bit line in a second plane orthogonal to the first plane, to facilitate electrical connection to the memory cells; a plurality of dual word lines non-orthogonal to the bit lines, wherein a dual word line includes a master word line at a first layer and a plurality of local word lines at a second layer, the local word lines being connected to the master word line of a common row via a plurality of spaced electrical connections, each local word line being connected to plural memory cells; wherein the plurality of bit line pairs run in substantially a zigzag-type pattern along the memory cell array in the first plane with respect to said dual word lines and said electrical connections run in substantially said zigzag-type pattern along the memory cell array.

Claim 13

Dependent Claim 209 words

A semiconductor memory, comprising: a memory cell array having a major surface in a first plane; a plurality of bit line pairs, wherein a bit line comprises a true bit line coupled to a plurality of true memory cells and an associated complementary bit line coupled to a plurality of complementary memory cells, the true bit line being periodically twisted with the associated complementary bit line such that the true bit line alternately overlies and underlies the complementary bit line in a second plane orthogonal to the first plane, to facilitate electrical connection to the memory cells; a plurality of dual word lines non-orthogonal to the bit lines, wherein a dual word line includes a master word line at a first layer and a plurality of local word lines at a second layer, the local word lines being connected to the master word line of a common row via a plurality of spaced electrical connections, each local word line being connected to plural memory cells; wherein the plurality of bit line pairs run in substantially a zigzag-type pattern along the memory cell array in the first plane with respect to said dual word lines and said electrical connections run in substantially said zigzag-type pattern along the memory cell array.

Claim 14

Dependent Claim 18 words

The memory of claim 11 wherein said electrical connections comprise electrical contacts between said first and second layers.

Claim 15

Dependent Claim 50 words

The memory of claim 11 wherein said bit line pairs generally run in alternating first and second slanted directions of said zigzag-type pattern with respect to the word lines, and the bit lines being twisted in three dimensions at portions of the pattern where a change in horizontal direction occurs.

Claim 16

Dependent Claim 19 words

The memory of claim 11 wherein said local word lines of a common row are separated from one another.

Claim 17

Dependent Claim 17 words

The memory of claim 11 wherein said local word lines of a common row are electrically continuous.

Claim 18

Dependent Claim 66 words

The memory of claim 11 wherein each bit line comprises a plurality of first portions and second portions, said first portions oriented in a direction orthogonal to said word lines and said second portions oriented at a first angle with respect to said word lines, wherein said first and second portions define said zigzag-type pattern running at a second angle with respect to said word lines.

Claim 19

Dependent Claim 14 words

The memory of claim 11 wherein said memory comprises a dynamic random access memory.

Claim 20

Dependent Claim 26 words

The memory of claim 11 wherein each memory cell occupies an area of about 6F 2 where F is the minimum feature size of memory elements.

Claim 21

Dependent Claim 19 words

The memory of claim 11 further comprising dummy bit lines on both sides of individual ones of said stitches.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-01-25	2002-07-27	2003-01-26	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-01-25	2006-07-27	2007-01-26	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-01-25	2010-07-27	2011-01-26	$7700.00	Window Closed / Lapsed

High density semiconductor memory having diagonal bit lines and dual word lines

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