Bit line arrangement for integrated circuits

Claim 2

A bit line arrangement for integrated circuits, comprising: a plurality of bit lines; each bit line of the plurality of bit lines having at least one contact that contacts at least one underlying conductive region and being widened to form a contact surface only in an area of said contact; contacts of adjacent bit lines being offset relative to one another thereby forming at least a 3-fold stagger; and a distance between bit line edges of two adjacent bit lines having everywhere a substantially constant value within a range of manufacturing tolerances.

Claim 3

The bit line arrangement according to claim 1, wherein the integrated circuit has a plurality of cells at least one of which has said at least one conductive region and wherein each bit line of the plurality of bit lines has a plurality of contacts succeeding one another in a row in a first direction, a respective contact of the plurality of contacts of each bit line contacting a respective underlying conductive region of at least one cell of the plurality of cells.

Claim 4

The bit line arrangement according to claim 2, wherein given a prescribed geometrical arrangement and size of the contacts of each of the bit lines of the plurality of bit lines, bit line edges of a given bit line of the plurality of bit lines represent, in segments, straight lines which have two gradients which differ at least in sign and differ from zero with respect to the first direction.

Claim 5

The bit line arrangement according to claim 3, wherein the straight lines are three straight lines g 1 , g 2 , g 3 that satisfy the following rule of construction: g 1 : mid-point 0 of a connecting section between contact K i and a contact, adjacent in the negative x-direction, of the i th bit line; the mid-point having coordinates, -2 R St ; 0; mid-point Q of a connecting section between contact K i-1 and a contact, adjacent in the positive x-direction, of an adjacent i-1 bit line; mid-point Q having coordinates -R St , R BL ; circle K Q around mid-point Q of radius r Q =b B +b Sp ; tangent to the circle k Q through mid-point 0; this tangent being a path axis of a bit line section being sought; g 1 being parallel to the path axis at a distance 1/2 b S ; g 2 : connecting section z between L a i and L c i-1 with mid-point Z; g 2 being perpendicular to connecting section z at a distance 1/2 b SP from mid-point Z; g 3 : g 3 being produced by translation of g 1 in the positive x-direction by 4R St ; where: b B : is the width of a bit line outside a contact surface; b Sp : is the distance between edges of adjacent bit lines; R BL : is a bit line raster in the y-direction; R St : is a stagger raster which is equal to the offset of the contacts of adjacent bit lines in the x-direction; n: is a whole number for an n-fold stagger of n+1 bit lines; K i : denotes the i=1 . . . n+1 contacts of the n+1 bit lines; and L a i -L d i : denotes corner points of the contacts K i , i=1, . . n+1.

Claim 6

The bit line arrangement according to claim 4, wherein the straight lines g 1 , g 2 , g 3 satisfy the following conditions: g j =a j +b j j=1, 2, 3 where a.sub.1 =(R.sub.BL sqr(R.sub.BL.sup.2 +R.sub.St.sup.2 -(b.sub.B +b.sub.Sp).sup.2 -R.sub.St (b.sub.B +b.sub.Sp))/(R.sub.St sqr(R.sub.BL.sup.2 +R.sub.St.sup.2 -(b.sub.B +b.sub.Sp).sup.2)-R.sub.BL (b.sub.B +b.sub.Sp)) b.sub.1 =b.sub.B /(2sqr(1+a.sub.1.sup.2))+2a.sub.1 R.sub.St +b.sub.b a.sub.1.sup.2 /(2sqr(1+a.sub.1.sup.2)) a.sub.2 =-(R.sub.St -x.sub.KL)/(R.sub.BL -y.sub.KL) b.sub.2 =R.sub.BL /2-b.sub.Sp /(2sqr(1+a.sub.2.sup.2))-R.sub.St a.sub.2 /2-b.sub.Sp a.sub.2.sup.2 /2sqr(1+a.sub.2.sup.2)) a.sub.3 =a.sub.1 b.sub.3 =b.sub.1 -4R.sub.St a.sub.1.

Claim 7

The bit line arrangement according to claim 2, wherein given a prescribed geometrical arrangement and size of the contacts, the bit line edges represent, in segments, straight lines which have at least three different gradients.

Claim 8

The bit line arrangement according to claim 6, wherein the straight lines are at right angles to connecting sections, the connecting sections connecting either a contact of one bit line to an adjacent contact of a neighboring bit line at their mid-points or connecting a contact of one bit line to an adjacent contact of a neighboring bit line at adjacent corner points thereof.

Claim 9

A bit line arrangement for integrated circuits, comprising: a plurality of bit lines and a plurality of cells; each bit line of the plurality of bit lines having a row of contacts in a first direction, each contact thereof contacting a conductive region of a respective cell and being widened to form a contact surface only in an area of said contacts; contacts of adjacent bit lines being offset relative to one another thereby forming at least a 3-fold stagger; a distance between bit line edges of two adjacent bit lines having everywhere a substantially constant value within a range of manufacturing tolerances; given a prescribed geometrical arrangement and size of the contacts, bit line edges of a given bit line of the plurality of bit lines represent, in segments, straight lines which have two gradients which differ at least in sign and differ from 0 with respect to the first direction, the straight lines being three straight lines g 1 , g 2 , g 3 that satisfy the following rule of construction: g 1 : mid-point 0 of a connecting section between contact K i and a contact, adjacent in the negative x-direction, of the i th bit line; the mid-point having coordinates, -2 R St ; 0; mid-point Q of a connecting section between contact K i-1 and a contact, adjacent in the positive x-direction, of an adjacent i-1 bit line; mid-point Q having coordinates -R St , R BL ; circle K Q around mid-point Q of radius r Q =b B +b Sp ; tangent to the circle k Q through mid-point 0; this tangent being a path axis of a bit line section being sought; g 1 being parallel to the path axis at a distance 1/2 b S ; g 2 : connecting section z between L a i and L c i-1 with mid-point Z; g 2 being perpendicular to connecting section z at a distance 1/2 b SP from mid-point Z; g 3 : g 3 being produced by translation of g 1 in the positive x-direction by 4R St ; where: b B : is the width of a bit line outside a contact surface; b Sp : is the distance between edges of adjacent bit lines; R BL : is a bit line raster in the y-direction; R St : is a stagger raster which is equal to the offset of the contacts of adjacent bit lines in the x-direction; n: is a whole number for an n-fold stagger of n+1 bit lines; K i : denotes the i=1 . . . n+1 contacts of the n+1 bit lines; and L a i -L d i : denotes corner points of the contacts K i , i=1, . . n+1.

Claim 10

A bit line arrangement for integrated circuits, comprising: a plurality of bit lines and a plurality of cells; each bit line of the plurality of bit lines having a row of contacts in a first direction, each contact thereof contacting a conductive region of a respective cell and being widened to form a contact surface only in an area of said contacts; contacts of adjacent bit lines being offset relative to one another thereby forming at least a 3-fold stagger; a distance between bit line edges of two adjacent bit lines having everywhere a substantially constant value within a range of manufacturing tolerances; given a prescribed geometrical arrangement and size of the contacts, bit line edges of a given bit line of the plurality of bit lines represent, in segments, straight lines which have two gradients which differ at least in sign and differ from 0 with respect to the first direction, the straight lines being three straight lines g 1 , g 2 , g 3 that satisfy the following rule of construction: g 1 : mid-point 0 of a connecting section between contact K i and a contact, adjacent in the negative x-direction, of the i th bit line; the mid-point having coordinates, -2 R St ; 0; mid-point Q of a connecting section between contact K i-1 and a contact, adjacent in the positive x-direction, of an adjacent i-1 bit line; mid-point Q having coordinates -R St , R BL ; circle K Q around mid-point Q of radius r Q =b B +b Sp ; tangent to the circle k Q through mid-point 0; this tangent being a path axis of a bit line section being sought; g 1 being parallel to the path axis at a distance 1/2 b S ; g 2 : connecting section z between L a i and L c i-1 with mid-point Z; g 2 being perpendicular to connecting section z at a distance 1/2 b SP from mid-point Z; g 3 : g 3 being produced by translation of g 1 in the positive x-direction by 4R St ; where: b B : is the width of a bit line outside a contact surface; b Sp : is the distance between edges of adjacent bit lines; R BL : is a bit line raster in the y-direction; R St : is a stagger raster which is equal to the offset of the contacts of adjacent bit lines in the x-direction; n: is a whole number for an n-fold stagger of n+1 bit lines; K i : denotes the i=1 . . . n+1 contacts of the n+1 bit lines; and L a i -L d i : denotes corner points of the contacts K i , i=1, . . n+1.

Claim 11

The bit line arrangement according to claim 8, wherein the straight lines g 1 , g 2 , g 3 satisfy the following conditions: g j =a j +b j j=1, 2, 3 where a.sub.1 =(R.sub.BL sqr(R.sub.BL.sup.2 +R.sub.St.sup.2 -(b.sub.B +b.sub.Sp).sup.2) -R.sub.St (b.sub.B +b.sub.Sp))/(R.sub.St sqr(R.sub.BL.sup.2 +R.sub.St.sup.2 -(b.sub.B +b.sub.Sp).sup.2)-R.sub.BL (b.sub.B +b.sub.Sp)) b.sub.1 =b.sub.B /(2sqr(1+a.sub.1.sup.2))+2a.sub.1 R.sub.St +b.sub.b a.sub.1.sup.2 /(2sqr(1+a.sub.1.sup.2)) a.sub.2 =-(R.sub.St -x.sub.KL)/(R.sub.BL -y.sub.KL) b.sub.2 =R.sub.BL /2-b.sub.Sp /(2sqr(1+a.sub.2.sup.2))-R.sub.St a.sub.2 /2-b.sub.Sp a.sub.2.sup.2 /2sqr(1+a.sub.2.sup.2)) a.sub.3 =a.sub.1 b.sub.3 =b.sub.1 -4R.sub.St a.sub.1.

Claim 12

A bit line arrangement for integrated circuits, comprising: a plurality of bit lines and a plurality of cells; each bit line of the plurality of bit lines having a row of contacts in a first direction, each contact thereof contacting a conductive region of a respective cell and being widened to form a contact surface only in an area of said contacts; contacts of adjacent bit lines being offset relative to one another thereby forming at least a 3-fold stagger; a distance between bit line edges of two adjacent bit lines having everywhere a substantially constant value within a range of manufacturing tolerances; and given a prescribed geometrical arrangement and size of the contacts, the bit line edges represent, in segments, straight lines which have at least three different gradients.

Claim 13

A bit line arrangement for integrated circuits, comprising: a plurality of bit lines and a plurality of cells; each bit line of the plurality of bit lines having a row of contacts in a first direction, each contact thereof contacting a conductive region of a respective cell and being widened to form a contact surface only in an area of said contacts; contacts of adjacent bit lines being offset relative to one another thereby forming at least a 3-fold stagger; a distance between bit line edges of two adjacent bit lines having everywhere a substantially constant value within a range of manufacturing tolerances; and given a prescribed geometrical arrangement and size of the contacts, the bit line edges represent, in segments, straight lines which have at least three different gradients.

Claim 14

The bit line arrangement according to claim 6, wherein the straight lines are at right angles to connecting sections, the connecting sections connecting either a contact of one bit line to an adjacent contact of a neighboring bit line at their mid-points or connecting a contact of one bit line to an adjacent contact of a neighboring bit line at adjacent corner points thereof.

Claim 15

The bit line arrangement according to claim 6, wherein for each of the straight lines, a respective straight line is perpendicular to a connecting section between respective first and second contacts of first and second bit lines, respectively, the respective connecting section connecting a predetermined location of said first contact to a predetermined location of said second contact.

Claim 16

The bit line arrangement according to claim 12, wherein said predetermined locations of said first and second contacts are mid-points of said first and second contacts.

Claim 17

The bit line arrangement according to claim 12, wherein each of said first and second contacts have corners and wherein said predetermined locations of said first and second contacts comprise a corner of said first contact that is the closest to a corner of said second contact.

Claim 18

The bit line arrangement according to claim 12, wherein said contacts are contact holes in an insulating layer.