Semiconductor memory device with improved contact layout

Claim 2

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells and these two memory cells of the memory cell pair having a common bit line contact area; wherein, in a unit region defined by word line Nos. "i" and "i + 1" and bit line Nos. "j" and "j + 4", there are provided bit line contact areas and storage capacitor contact areas with a ratio of 1:2 between the number of the bit line contact areas and the storage capacitor contact areas.

Claim 3

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line; the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells and these two memory cells of the memory cell having a common bit line contact area; wherein bit line contact areas of the memory cell pairs connected to the adjacent bit lines are located on the opposite sides of a word line, and the memory cell pairs are arranged in the same direction.

Claim 4

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line; the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells and these two memory cells of the memory cell having a common bit line contact area; wherein bit line contact areas of the memory cell pairs connected to the adjacent bit lines are located on the opposite sides of a word line, and the memory cell pairs are arranged in the same direction.

Claim 5

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells and these two memory cells of the memory cell having a common bit line contact area; wherein bit line contact areas of the memory cell pairs connected to the adjacent bit lines are located. on the opposite sides of a word line, and each of the memory cell pairs is arranged in an oblique direction.

Claim 6

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells and these two memory cells of the memory cell having a common bit line contact area; wherein bit line contact areas of the memory cell pairs connected to the adjacent bit lines are located. on the opposite sides of a word line, and each of the memory cell pairs is arranged in an oblique direction.

Claim 7

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearly memory cells and these two memory cells of the memory cell having a common bit line contact area; wherein a unit memory cell array has a parallelogram configuration.

Claim 8

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearly memory cells and these two memory cells of the memory cell having a common bit line contact area; wherein a unit memory cell array has a parallelogram configuration.

Claim 9

A device according to claim 4, wherein one side of the parallelogram is parallel with one side of a semiconductor chip on which the semiconductor memory device is arranged.

Claim 10

A device according to claim 5, wherein the unit memory cell array is divided by a straight line parallel with one side of the unit memory cell array into portions the number of which is an integer multiple of two, and the divided memory cell array constitutes a mirror image symmetry by inversion.

Claim 11

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells and these two memory cells of the memory cell having a common bit line contact area; wherein a bit line contact area of a memory cell pair connected to a bit line and a bit line contact area of a memory cell pair connected to a bit line adjacent in one side of said bit line are arranged on the opposite sides of two adjacent word lines, bit line contact areas of memory cell pairs connected to a bit line adjacent to the other side of said bit line are arranged on the opposite side of a word line, the distribution direction of a memory cell pair connected to a bit line intersects the distribution direction of a memory cell pair connected to a bit line adjacent to one side of said bit line, and is parallel with the distribution direction of a memory cell pair connected to a bit line adjacent to the other side of said bit line, and bit lines having bit line contact areas placing two word lines therebetween are connected as a bit line pair to the same sense amplifier.

Claim 12

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells and these two memory cells of the memory cell having a common bit line contact area; wherein a bit line contact area of a memory cell pair connected to a bit line and a bit line contact area of a memory cell pair connected to a bit line adjacent in one side of said bit line are arranged on the opposite sides of two adjacent word lines, bit line contact areas of memory cell pairs connected to a bit line adjacent to the other side of said bit line are arranged on the opposite side of a word line, the distribution direction of a memory cell pair connected to a bit line intersects the distribution direction of a memory cell pair connected to a bit line adjacent to one side of said bit line, and is parallel with the distribution direction of a memory cell pair connected to a bit line adjacent to the other side of said bit line, and bit lines having bit line contact areas placing two word lines therebetween are connected as a bit line pair to the same sense amplifier.

Claim 13

A device according to claim 7, wherein a storage capacitor is formed on the bit line.

Claim 14

A device according to claim 7, wherein a bit line is formed on the storage capacitor.

Claim 15

A device according to claim 9, wherein the memory cell pair is arranged in a direction parallel with the bit line.

Claim 16

A device according to claim 9, wherein the memory cell pair is arranged in an oblique direction with regard to the bit line.

Claim 17

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells and these two memory cells of the memory cell having a common bit line contact area; wherein a storage capacitor is formed on the bit line, bit line contact areas are arranged on one side of the bit line pair connected to the same sense amplifier, memory cell pairs connected to a bit line place two word lines therebetween, and the position of a bit line contact area of a bit line connected to the next sense amplifier is displaced with regard to the position of a bit line contact area of a bit line connected to the preceding sense amplifier.

Claim 18

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines intersected by said plurality of word lines; and a plurality of memory cells located at intersections of the word lines and the bit lines, each of said memory cells comprising a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of said transfer transistor being connected to a word line, the source of said transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor; a memory cell pair being formed by two nearby memory cells and these two memory cells of the memory cell having a common bit line contact area; wherein a storage capacitor is formed on the bit line, bit line contact areas are arranged on one side of the bit line pair connected to the same sense amplifier, memory cell pairs connected to a bit line place two word lines therebetween, and the position of a bit line contact area of a bit line connected to the next sense amplifier is displaced with regard to the position of a bit line contact area of a bit line connected to the preceding sense amplifier.

Claim 19

A device according to claim 12, wherein two memory cells constituting a memory cell pair connected to a bit line are arranged on both sides of the bit line.

Claim 20

A device according to claim 13, wherein memory cell pairs connected to a bit line are arranged in the same oblique direction with regard to the bit line.

Claim 21

A device according to claim 13, wherein the distribution direction of a memory cell pair connected to a bit line intersects the distribution direction of a memory cell pair connected to the second adjacent bit line.

Claim 22

A device according to claim 12, wherein the two memory cells constituting a memory cell pair connected to a bit line are arranged on one side of the bit line, and

Claim 23

the two memory cells constituting memory cell pairs placing two word lines therebetween are arranged on both sides of the bit line.

Claim 24

the two memory cells constituting memory cell pairs placing two word lines therebetween are arranged on both sides of the bit line.

Claim 25

A device according to claim 16, wherein a memory cell pair connected to a bit line is in a T shape or in a V shape having a bit line contact area at the center thereof.

Claim 26

A device according to claim 12, wherein the device is divided into a first memory cell array range in which the memory cell pairs are connected to a bit line and a second memory cell array range in which the memory cell pairs are connected to a bit line adjacent to the above-mentioned bit line.