Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a semiconductor substrate; a plurality of bit lines arranged on said semiconductor substrate and extending generally in a first direction; a plurality of word lines arranged on said semiconductor substrate and extending so as to intersect said bit lines; a plurality of cell regions formed on said semiconductor substrate, each of said cell regions extending so as to be crossed by one of said bit lines and at least two adjacent word lines, and wherein each cell region on a portion of said substrate is respectively arranged to extend in a same direction; and a plurality of memory cell pairs respectively formed in each of said cell regions, each of said memory cell pairs including first and second stacked capacitors having respective storage electrodes, wherein each of said memory cell pairs includes a first contact coupled to said storage electrode of said first capacitor, a second contact coupled to the bit line crossing the associated cell region and a third contact coupled to said storage electrode of said second capacitor, said first and third contacts each being disposed at a region on said semiconductor substrate surrounded by two adjacent bit lines and two adjacent word lines, wherein successive of said second contacts of any one of said bit lines are separated by a predetermined pitch and the contacts of a first bit line are shifted by approximately 1/2 n pitch along said first direction from said contacts of a second adjacent bit line, and wherein n is a natural number greater than or equal to 2.

Claim 3

The semiconductor memory device according to claim 1, wherein each of said cell regions is crossed by one of said bit lines and at least two adjacent word lines non-perpendicularly.

Claim 4

The semiconductor memory device according to claim 1, wherein n is equal to 2.

Claim 5

The semiconductor memory device according to claim 1, wherein n is equal to 3.

Claim 6

The semiconductor memory device according to claim 4, wherein said bit lines and word lines are arranged in a wave-like pattern.

Claim 7

The semiconductor memory device according to claim 1, wherein each of said memory cell pairs includes two field effect transistors, each transistor comprising respective source and drain regions.

Claim 8

The semiconductor memory device according to claim 6, wherein one of said source and drain regions in each of said transistors comprises a common region.

Claim 9

The semiconductor memory device according to claim 7, wherein said second contact is coupled to said common region.

Claim 10

The semiconductor memory device according to claim 1, wherein said cell regions have parallel longitudinal axes and the longitudinal axis of each of said cell regions is crossed by one of said bit lines and at least two adjacent word lines.

Claim 11

The semiconductor memory device according to claim 9, wherein said longitudinal axis of each of said cell regions is crossed by one of said bit lines and said at least two adjacent word lines non-perpendicularly.

Claim 12

The semiconductor memory device according to claim 1, wherein said cell regions are surrounded by a field insulating film.

Claim 13

The semiconductor memory device according to claim 1, wherein each of said first and second stacked capacitors includes an insulating film provided on said storage electrode and a plate electrode formed on said insulating film.

Claim 14

The semiconductor memory device according to claim 1, wherein each of said storage electrodes has an elongated pattern which overlaps an intersection of a bit line and a word line.

Claim 15

The semiconductor memory device according to claim 13, wherein each storage electrode has a longitudinal axis different from a longitudinal axis of its associated cell region.

Claim 16

The semiconductor memory device according to claim 1, wherein a line width of at least one of said bit lines and word lines is made narrower in a portion near said storage electrode.

Claim 17

The semiconductor memory device according to claim 1, wherein a bit line sense amplifier is connected to ends of two bit lines so that said two bit lines provide a complementary pair arrangement.

Claim 18

The semiconductor memory device according to claim 1, wherein a portion of at least one of said first and third contacts is disposed so as to overlap at least one of said two adjacent bit lines.

Claim 19

The semiconductor memory device according to claim 1, wherein a portion of at least one of said first and third contacts is disposed so as to overlap at least one of said two adjacent word lines.

Claim 20

The semiconductor memory device according to claim 1, wherein a portion of at least one of said first and third contacts is disposed so as to overlap at least one of said two adjacent bit lines and at least one of said two adjacent word lines.

Claim 21

A semiconductor memory device comprising: a semiconductor body; M bit lines arranged on said semiconductor body; N word lines arranged on said semiconductor body and intersecting said bit lines; a first memory cell pair formed on said semiconductor body and having a first contact between an n and an (n+1) word line and an m and an (m+1) bit line, a second contact between an (n+2) and an (n+3) word line and the (m+1) and an (m+2) bit line, and a third contact at the (m+1) bit line; a second memory cell pair formed on said semiconductor body and having a first contact between the (n+2) and the (n+3) word line and the (m+2) and an (m+3) bit line; and a third memory cell pair formed on said semiconductor body and having a first contact between the (n+3) and an (n+4) word line and the (m+1) and the (m+2) bit lines.

Claim 22

A semiconductor memory device comprising: a semiconductor body; M bit lines arranged on said semiconductor body; N word lines arranged on said semiconductor body and intersecting said bit lines; a first memory cell pair formed on said semiconductor body and having a first contact between an n and an (n+1) word line and an m and an (m+1) bit line, a second contact between an (n+2) and an (n+3) word line and the (m+1) and an (m+2) bit line, and a third contact at the (m+1) bit line; a second memory cell pair formed on said semiconductor body and having a first contact between the (n+2) and the (n+3) word line and the (m+2) and an (m+3) bit line; and a third memory cell pair formed on said semiconductor body and having a first contact between the (n+3) and an (n+4) word line and the (m+1) and the (m+2) bit lines.

Claim 23

The semiconductor memory device according to claim 20, wherein said N word lines extend in a first direction and the M bit lines extend in a second direction perpendicular to the first direction.

Claim 24

The semiconductor memory device according to claim 20, wherein a portion of at least one of said first contacts of said first, second and third memory cell pairs is disposed so as to overlap at least one of adjacent bit lines.

Claim 25

The semiconductor memory device according to claim 20, wherein a portion of at least one of said first contacts of said first, second and third memory cell pairs is disposed so as to overlap at least one of adjacent word lines.

Claim 26

A semiconductor memory device, comprising: memory cell pairs, the memory cells of said memory cell pairs each including first and second terminal regions and having a storage electrode associated therewith; word lines arranged to overlap channel regions defined by the first and second terminal regions of said memory cells; bit lines arranged to intersect said word lines; first contacts coupling said bit lines to the first terminal region of both memory cells of said memory cell pairs, wherein successive of said first contacts of any bit line are separated by a predetermined pitch and the first contacts of a first bit line are shifted by approximately 1/2 n pitch from the contacts of a second adjacent bit line, where n is a natural number greater than or equal to 2; and second and third contacts respectively coupling the second terminal regions of each memory cell to its associated storage electrode, the second and third contacts of each memory cell pair having a bit line disposed therebetween.

Claim 27

A semiconductor memory device, comprising: memory cell pairs, the memory cells of said memory cell pairs each including first and second terminal regions and having a storage electrode associated therewith; word lines arranged to overlap channel regions defined by the first and second terminal regions of said memory cells; bit lines arranged to intersect said word lines; first contacts coupling said bit lines to the first terminal region of both memory cells of said memory cell pairs, wherein successive of said first contacts of any bit line are separated by a predetermined pitch and the first contacts of a first bit line are shifted by approximately 1/2 n pitch from the contacts of a second adjacent bit line, where n is a natural number greater than or equal to 2; and second and third contacts respectively coupling the second terminal regions of each memory cell to its associated storage electrode, the second and third contacts of each memory cell pair having a bit line disposed therebetween.

Claim 28

The semiconductor memory device according to claim 24, wherein a portion of at least one of said second and third contacts is disposed so as to overlap at least one of adjacent bit lines.

Claim 29

The semiconductor memory device according to claim 24, wherein a portion of at least one of said second and third contacts is disposed so as to overlap at least one of adjacent word lines.

Claim 30

A semiconductor memory device formed on a substrate, comprising: memory cell pairs, the memory cells of said memory cell pairs each including a transistor having first and second terminal regions and a capacitor having a storage electrode; word lines arranged to overlap channel regions defined by the first and second terminal regions of said transistors; a plurality of sense amplifiers; a plurality of bit line pairs, each bit line pair comprising first and second bit lines connected to one of said sense amplifiers and arranged to intersect said word lines; first contacts respectively coupling said bit lines to the first terminal region of both transistors of said respective memory cell pairs, wherein successive of said first contacts are separated by a predetermined pitch and the first contacts of a first bit line are shifted by approximately 1/2 n pitch from the contacts of a second adjacent bit line, where n is a natural number greater than or equal to 2; second contacts coupling the second terminal of one transistor of each respective memory cell pair to its associated storage electrode; and third contacts coupling the second terminal of the other transistor of each respective memory cell pair to its associated storage electrode, the second and third contacts of each respective memory cell pair having a bit line disposed therebetween.

Claim 31

A semiconductor memory device formed on a substrate, comprising: memory cell pairs, the memory cells of said memory cell pairs each including a transistor having first and second terminal regions and a capacitor having a storage electrode; word lines arranged to overlap channel regions defined by the first and second terminal regions of said transistors; a plurality of sense amplifiers; a plurality of bit line pairs, each bit line pair comprising first and second bit lines connected to one of said sense amplifiers and arranged to intersect said word lines; first contacts respectively coupling said bit lines to the first terminal region of both transistors of said respective memory cell pairs, wherein successive of said first contacts are separated by a predetermined pitch and the first contacts of a first bit line are shifted by approximately 1/2 n pitch from the contacts of a second adjacent bit line, where n is a natural number greater than or equal to 2; second contacts coupling the second terminal of one transistor of each respective memory cell pair to its associated storage electrode; and third contacts coupling the second terminal of the other transistor of each respective memory cell pair to its associated storage electrode, the second and third contacts of each respective memory cell pair having a bit line disposed therebetween.

Claim 32

The semiconductor memory device according to claim 27, wherein said bit line pairs comprise: first and second bit lines; and third and fourth bit lines, said third bit line being located between said first and second bit lines.

Claim 33

The semiconductor memory device according to claim 27, wherein a portion of at least one of said second and third contacts is disposed so as to overlap at least one of adjacent bit lines.

Claim 34

The semiconductor memory device according to claim 27, wherein a portion of at least one of said second and third contacts is disposed so as to overlap at least one of adjacent word lines.

Claim 35

A semiconductor memory device, comprising: a semiconductor body of a first conductivity type; word lines extending on said substrate and insulated therefrom; bit lines intersecting said word lines and insulated therefrom; a plurality of memory cells arranged in pairs, each memory cell including a transistor and a capacitor and each memory cell pair comprising: first, second, and third impurity doped regions of a second conductivity type opposite to the first conductivity type formed in said semiconductor body, said first impurity doped region electrically connected to one of said bit lines, said first and second impurity doped regions and a respective portion of a first word line forming the transistor of one memory cell of said memory cell pair and said first and third impurity doped regions and a respective portion of a second word line different than the first word line forming the transistor of the other memory cell of said memory cell pair; a first electrode connected to said second impurity doped region for forming a storage electrode of the capacitor of one memory cell of said memory cell pair; and a second electrode connected to said third impurity doped region for forming a storage electrode of the capacitor of the other memory cell of said memory cell pair, wherein successive connections of the first impurity doped regions of said memory cell pairs to a respective bit line are separated by a predetermined pitch and the connections to a first bit line are shifted by approximately 1/2 n pitch from the connections to a second adjacent bit line, where n is a natural number greater than or equal to 2, and a bit line is disposed between the connection of the first storage electrode to the second impurity doped region and the connection of the second storage electrode to third impurity doped region of each memory cell pair.

Claim 36

A semiconductor memory device, comprising: a semiconductor body of a first conductivity type; word lines extending on said substrate and insulated therefrom; bit lines intersecting said word lines and insulated therefrom; a plurality of memory cells arranged in pairs, each memory cell including a transistor and a capacitor and each memory cell pair comprising: first, second, and third impurity doped regions of a second conductivity type opposite to the first conductivity type formed in said semiconductor body, said first impurity doped region electrically connected to one of said bit lines, said first and second impurity doped regions and a respective portion of a first word line forming the transistor of one memory cell of said memory cell pair and said first and third impurity doped regions and a respective portion of a second word line different than the first word line forming the transistor of the other memory cell of said memory cell pair; a first electrode connected to said second impurity doped region for forming a storage electrode of the capacitor of one memory cell of said memory cell pair; and a second electrode connected to said third impurity doped region for forming a storage electrode of the capacitor of the other memory cell of said memory cell pair, wherein successive connections of the first impurity doped regions of said memory cell pairs to a respective bit line are separated by a predetermined pitch and the connections to a first bit line are shifted by approximately 1/2 n pitch from the connections to a second adjacent bit line, where n is a natural number greater than or equal to 2, and a bit line is disposed between the connection of the first storage electrode to the second impurity doped region and the connection of the second storage electrode to third impurity doped region of each memory cell pair.

Claim 37

The semiconductor memory device according to claim 31, wherein said second and third impurity diffused regions comprise source regions and said first impurity diffused region comprises a drain region common to the transistors of said memory cell pair.

Claim 38

The semiconductor memory device according to claim 31, wherein said word lines include first word line portions having a first width WA and second word line portions having a second width Wa smaller than the first width WA, said second word line portions located near connections of said second and third impurity diffused regions to said storage electrodes.

Claim 39

The semiconductor memory device according to claim 31, wherein said bit lines include first bit line portions having a first width WB and second bit line portions having a second width Wb smaller than the first width WB, said second bit line portions located near connections of said second and third impurity diffused regions to said storage electrodes.

Claim 40

The semiconductor memory device according to claim 31, wherein said bit lines comprises folded bit lines.

Claim 41

The semiconductor memory device according to claim 35, wherein the connections to a first bit line are shifted by approximately 1/8 pitch from the connections to a second adjacent bit line.

Claim 42

The semiconductor memory device according to claim 31, wherein each memory cell includes a transistor and a stacked capacitor.

Claim 43

The semiconductor memory device according to claim 31, further comprising: an insulating film on said first and second storage electrodes; and a plate electrode on said insulating film.

Claim 44

The semiconductor memory device according to claim 31, further comprising: a first sense amplifier connected to first and second bit lines; and a second sense amplifier connected to third and fourth bit lines, wherein said third bit line is disposed between said first and second bit lines.