Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To increase the charge accumulation capacitance of a capacitor as well to contrive reduction of a soft error by a method wherein the area of the electrode layer of the capacitor, to be used for information accumulation utilizing the extended space of the selective signal line, in increased in a DRAM. CONSTITUTION:A DRAM memory cell M is composed of a cell selecting MISFETQs and an information accumulating capacitor C of a stacked structure. In this DRAM memory cell, a set of complementary data line DL and a selective signal line YSL, with which said data line DL will be selected, are extended in the same direction. Then, the lower side electrode layer 13, constituting the above-mentioned capacitor C, is extended to the position where the electrode layer 13 will be overlapped with the selective signal line YSL. As a result, the area of the lower side electrode layer of the information accumulating capacitor C can be increased, the amount of the charge accumulation of the capacitor can also be increased, and the soft error of the DRAM can be reduced.

Inventors

• 👤 Jun Murata

Bibliographic Details