US5034920A
Expired / Lapsed
US
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Cross point array memory device
Assignee: Texas Instruments Inc
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Filing: 1990-05-03
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Granted: 1991-07-23
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Expires: 2010-05-03
Abstract
Abstract A memory array layout using complementary bitlines connected to a single sense amplifier. Extending from the sense amplifier, bitlines which are unconnected are extended to the middle of the array. One complementary bitline is then connected to a series of memory cells extending away from the sense amplifier. The other complementary bitline loops back and is connected to a set of memory cells extending back toward the sense amplifier. The first bitline section extending from the sense amplifier may be advantageously formed in a metal layer above the substrate thereby occupying no space in the substrate itself. All noise generated on the first sections of the bitlines will be canceled by the complementary parallel structure of the bitlines. Because the second sections of the bitlines are laterally separated, a wordline passing across each of the second sections addresses a singel memory cell. Therefore an optimally compact cross-point memory array may be fabricated. Using the described techniques an optimally compact array having an improved signal to noise characteristic may be fabricated.
Inventors
- 👤 Robert N. Rountree
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:35
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
430 words
A cross point array memory device, comprising: a first sense amplifier having first and second input terminals; a second sense amplifier having first and second input terminals; a first column of memory cells disposed between said first and second sense amplifiers, said first column including a first subset of memory cells, said first subset being a contiguous group of memory cells nearest said first sense amplifier, said first column also having a second subset, said second subset being those memory cells of said first column not included in said first subset; a second column of memory cells disposed between said first and second sense amplifiers, said second column including a first subset of memory cells, said first subset being a contiguous group of memory cells nearest said first sense amplifier and said first subset having the same number of memory cells as said first said subset of said first column, said second column also including a second subset consisting of those memory cells of said second column not in said first subset and said second subset having the same number of memory cells as said second subset of said first column; a plurality of row lines, said row lines comprising conductors connected to a control terminal of no more than one memory cell in each of said first and second columns; a first partial bitline comprising a conductive line disposed parallel to said first subset of said first column having the end of said first partial bitline nearest said first sense amplifier electrically connected to said first input terminal of said first sense amplifier; a second partial bitline comprising a conductive line disposed parallel to said second subset of said first column electrically connected to each of said memory cells of said second subset of said first column and having the end of said second partial bitline nearest to said first sense amplifier connected to the end of said first partial bitline disposed away from said first sense amplifier; a third partial bitline comprising a conductive line disposed parallel to said first subset of said first column having the end of said bitline nearest said first sense amplifier connected to said second input terminal of said first sense amplifier; and a fourth partial bitline comprising a conductive line disposed parallel to said first subset of said first column electrically connected to each memory cell in said first subset of said first column, the end of said fourth partial bitline nearest said second sense amplifier being electrically connected to the end of said third partial bitline nearest said second sense amplifier.
Claim 2
Dependent Claim
430 words
A cross point array memory device, comprising: a first sense amplifier having first and second input terminals; a second sense amplifier having first and second input terminals; a first column of memory cells disposed between said first and second sense amplifiers, said first column including a first subset of memory cells, said first subset being a contiguous group of memory cells nearest said first sense amplifier, said first column also having a second subset, said second subset being those memory cells of said first column not included in said first subset; a second column of memory cells disposed between said first and second sense amplifiers, said second column including a first subset of memory cells, said first subset being a contiguous group of memory cells nearest said first sense amplifier and said first subset having the same number of memory cells as said first said subset of said first column, said second column also including a second subset consisting of those memory cells of said second column not in said first subset and said second subset having the same number of memory cells as said second subset of said first column; a plurality of row lines, said row lines comprising conductors connected to a control terminal of no more than one memory cell in each of said first and second columns; a first partial bitline comprising a conductive line disposed parallel to said first subset of said first column having the end of said first partial bitline nearest said first sense amplifier electrically connected to said first input terminal of said first sense amplifier; a second partial bitline comprising a conductive line disposed parallel to said second subset of said first column electrically connected to each of said memory cells of said second subset of said first column and having the end of said second partial bitline nearest to said first sense amplifier connected to the end of said first partial bitline disposed away from said first sense amplifier; a third partial bitline comprising a conductive line disposed parallel to said first subset of said first column having the end of said bitline nearest said first sense amplifier connected to said second input terminal of said first sense amplifier; and a fourth partial bitline comprising a conductive line disposed parallel to said first subset of said first column electrically connected to each memory cell in said first subset of said first column, the end of said fourth partial bitline nearest said second sense amplifier being electrically connected to the end of said third partial bitline nearest said second sense amplifier.
Claim 3
Dependent Claim
39 words
A device as in claim 1 wherein said first and third partial bitlines comprise deposited metal formed on an insulating layer, said insulating layer electrically separating said first and third partial bitlines from said second and fourth partial bitlines.
Claim 4
Dependent Claim
27 words
A device as in claim 1 formed over a semiconductive substrate and wherein said second and fourth partial bitlines comprise highly doped regions in said semiconductive substrate.
Claim 5
Dependent Claim
15 words
A device as in claim 1 wherein said device is a dynamic random access memory.
Claim 6
Dependent Claim
32 words
A device as in claim 1 wherein said first partial bitline is positioned vertically above said second partial bitline and said third partial bitline is positioned vertically above said fourth partial bitline.
Claim 7
Dependent Claim
213 words
An integrated circuit device formed on a semiconductor material with first and second conductor levels and including a cross-point array of memory cells formed in the semiconductor material comprising: first and second sense amplifiers; a folded bitline including first, second, third and fourth conductive segments, the first and second segments formed on the first conductor level, the third and fourth segments formed on the second conductor level, the first and second segments each including first and second ends, each first end connected to the first sense amplifier, the first and second segments extending toward and second sense amplifier, the third segment having a first end connected to the second end of the first segment, the fourth segment having a first end connected to the second end of the second segment; a plurality of memory cells formed along said bitline, including a first subset of cells electrically connected to the third segment and a second subset of cells electrically connected to the fourth segment; a plurality of row lines positioned between the first and second sense amplifiers each electrically connected to a memory cell formed along said bitline, wherein for every crossing of every row line with either the third or fourth segment there is a corresponding one of said plurality of memory cells.
Claim 8
Dependent Claim
213 words
An integrated circuit device formed on a semiconductor material with first and second conductor levels and including a cross-point array of memory cells formed in the semiconductor material comprising: first and second sense amplifiers; a folded bitline including first, second, third and fourth conductive segments, the first and second segments formed on the first conductor level, the third and fourth segments formed on the second conductor level, the first and second segments each including first and second ends, each first end connected to the first sense amplifier, the first and second segments extending toward and second sense amplifier, the third segment having a first end connected to the second end of the first segment, the fourth segment having a first end connected to the second end of the second segment; a plurality of memory cells formed along said bitline, including a first subset of cells electrically connected to the third segment and a second subset of cells electrically connected to the fourth segment; a plurality of row lines positioned between the first and second sense amplifiers each electrically connected to a memory cell formed along said bitline, wherein for every crossing of every row line with either the third or fourth segment there is a corresponding one of said plurality of memory cells.
Claim 9
Dependent Claim
31 words
The device of claim 6 wherein a first group of said row lines crosses only the third segment and a second group of said row lines crosses only the fourth segment.
Claim 10
Dependent Claim
31 words
The device of claim 6 wherein the number of row lines positioned between the first and second sense amplifiers is equal to the number of cells electrically connected to said bitline.
Claim 11
Dependent Claim
147 words
The device of claim 6 further including: a second folded bitline including first, second, third and fourth conductive segments, the first and second segments formed on the first conductor level, the third and fourth segments formed on the second conductor level, the first and second segments each including first and second ends, each first end connected to the second sense amplifier, the first and second segments extending toward the first sense amplifier, the third segment having a first end connected to the second end of the first segment, the fourth segment having a first end connected to the second end of the second segment; a second plurality of memory cells formed along said second bitline, including a first subset of cells electrically connected to the third segment of said second bitline and a second subset of cells electrically connected to the fourth segment of said second bitline.
Claim 12
Dependent Claim
47 words
The device of claim 9 wherein, for all row lines between the first and second sense amplifiers, for every crossing of a row line with either the third or fourth segment of said second bitline there is a corresponding one of said second plurality of memory cells.
Claim 13
Dependent Claim
18 words
The device of claim 6 wherein said memory cells each comprise a storage capacitor and a pass transistor.
Claim 14
Dependent Claim
32 words
The device of claim 6 wherein said semiconductor material comprises a semiconductor substrate having an upper surface with the second conductor level formed as a heavily doped diffusion region in said surface.
Claim 15
Dependent Claim
48 words
The device of claim 6 wherein: the second conductor level is formed in said semiconductor material and the first conductor level is formed with a layer of polysilicon over said semiconductor material; and an insulative layer is formed between the second conductive level and the first conductive level.
Claim 16
Dependent Claim
52 words
The device of claim 6 wherein: said memory cells each comprise a storage capacitor and a pass transistor; and said row lines are formed in a third conductor level, separate and distinct from the first and second conductor levels, comprising polysilicon, said third level including a gate region for each pass transistor.
Claim 17
Dependent Claim
139 words
A cross point array memory device, comprising: A. an array of memory cells arranged in rows and columns, each cell including a control terminal and a data terminal; B. plural wordlines overlying said array in parallel arrangement, each wordline being generally aligned with one row of memory cells and being connected to the control terminal of every memory cell in that row at each column; and C. plural pairs of adjacent complementary bitlines overlying said array, each pair being generally aligned with one column of memory cells and being connected to the data terminal of every memory cell in that column, one of said bitlines of each pair of complementary bitlines being connected to one continuous series of memory cells and the other bitline of each pair of complementary bitlines being connected to another continuous series of memory cells.
Claim 18
Dependent Claim
139 words
A cross point array memory device, comprising: A. an array of memory cells arranged in rows and columns, each cell including a control terminal and a data terminal; B. plural wordlines overlying said array in parallel arrangement, each wordline being generally aligned with one row of memory cells and being connected to the control terminal of every memory cell in that row at each column; and C. plural pairs of adjacent complementary bitlines overlying said array, each pair being generally aligned with one column of memory cells and being connected to the data terminal of every memory cell in that column, one of said bitlines of each pair of complementary bitlines being connected to one continuous series of memory cells and the other bitline of each pair of complementary bitlines being connected to another continuous series of memory cells.
Claim 19
Dependent Claim
28 words
The memory device of claim 15 in which said pairs of bitlines each are of substantially equal length and are connected to substantially equal numbers of memory cells.
Claim 20
Dependent Claim
63 words
The memory device of claim 15 in which said pairs of complementary bitlines each have a first portion and a second portion, said first portions extending substantially along one another and being free of connections to said memory cells, and said second portions extending substantially away from one another and respectively being connected to said one and another continuous groups of memory cells.
Claim 21
Dependent Claim
39 words
The memory device of claim 17 including a semiconductor substrate carrying plural layers of material, said first portions are formed in an upper layer and said second portions are formed in a lower layer and are connected by vias.
Claim 22
Dependent Claim
20 words
The memory device of claim 18 in which said first portions are formed in a metal layer above said substrate.
Claim 23
Dependent Claim
52 words
The memory device of claim 17 in which said second portion of one bitline of said pair extends substantially in the same direction from said first portion of said one bitline, and said second portion of the other bitline of said pair loops back along said first portion of said other bitline.
Claim 24
Dependent Claim
41 words
The memory device of claim 15 including plural sense amplifiers, each pair of bitlines being connected to and extending from one of said sense amplifiers, and said bitlines from each sense amplifier being interleaved with said bitlines from other sense amplifier.
Claim 25
Dependent Claim
14 words
The memory device of claim 21 in which said bitlines interleave on alternating columns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-22 | 1995-01-21 | 1995-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-22 | 1999-01-21 | 1999-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-22 | 2003-01-21 | 2003-07-23 | $7700.00 | Window Closed / Lapsed |