US6731147B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and architecture for self-clocking digital delay locked loop
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 2001-10-29
•
Granted: 2004-05-04
•
Expires: 2021-10-29
Abstract
Abstract An apparatus comprising a delay line and a control circuit. The delay line may be configured to generate an output signal in response to an input signal and one or more control signals. The delay line may be self-clocked. A phase of the output signal may be adjusted in response to the one or more control signals. The control circuit may be configured to generate the one or more control signals in response to the input signal and the output signal.
Inventors
- 👤 Timothy E. Fiscus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:55
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/0818; H03L7/087
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
113 words
An apparatus comprising: a delay chain configured to generate an output signal and a plurality of clock signals in response to an input signal and delay a plurality of select signals; a shift register configured to generate said plurality of select signals in response to said one or more first control signals and a said response to one or more first control signals and a said plurality of clock signals, wherein a phase of said output signal is adjusted in response to said one or more first control signals; and a control circuit configured to generate said one or more first control signals in response to said input signal and said output signal.
Claim 2
Independent Claim
113 words
An apparatus comprising: a delay chain configured to generate an output signal and a plurality of clock signals in response to an input signal and delay a plurality of select signals; a shift register configured to generate said plurality of select signals in response to said one or more first control signals and a said response to one or more first control signals and a said plurality of clock signals, wherein a phase of said output signal is adjusted in response to said one or more first control signals; and a control circuit configured to generate said one or more first control signals in response to said input signal and said output signal.
Claim 3
Dependent Claim
29 words
The apparatus according to claim 1 , wherein said chain comprises a plurality of delay elements, each delay element configured to generate one of said plurality of clock signals.
Claim 4
Dependent Claim
22 words
The apparatus according to claim 2 , wherein said each of said delay elements comprises a delay cell and a CMOS pass-gate.
Claim 5
Dependent Claim
15 words
The apparatus according to claim 3 , wherein said delay cell comprises a CMOS inverter.
Claim 6
Dependent Claim
50 words
The apparatus according to claim 1 , wherein said shift register comprises a plurality of register elements, each of said register elements configured to generate one of said plurality of select signals in response to said one or more first control signals and one of said plurality of clock signals.
Claim 7
Dependent Claim
30 words
The apparatus according to claim 5 , wherein each of said register elements is configured to receive said one of said plurality of clock signals from a corresponding delay element.
Claim 8
Dependent Claim
43 words
The apparatus according to claim 5 , wherein one or more of said register elements are configured to receive one said plurality of select signals from a previous register element and another of said plurality of select signals from a next register element.
Claim 9
Dependent Claim
18 words
The apparatus according to claim 5 , wherein each of said register elements comprises one or more latches.
Claim 10
Dependent Claim
56 words
The apparatus according to claim 1 , wherein said control circuit comprises: a delay adjustment circuit configured to generate said one or more first control signals in response to said input signal and a feedback signal; and a delay circuit configured to generate said feedback signal in response to said output signal and a predetermined delay.
Claim 11
Dependent Claim
68 words
The apparatus according to claim 9 , wherein said delay adjustment circuit comprises: a digital loop filter circuit configured to generate said one or more first control signals in response to a said feedback signal, a second control signal and a third control signal; and a phase detector circuit configured to generate said second and third control signals in response to said input signal and said feedback signal.
Claim 12
Dependent Claim
38 words
The apparatus according to claim 10 , wherein said digital loop filter circuit comprises a digital logic circuit configured to control said delay line in response to a phase difference between said input signal and said feedback signal.
Claim 13
Dependent Claim
36 words
The apparatus according to claim 10 , wherein said phase detector circuit is configured to generate said second and third control signals in response to a phase difference between said input signal and said feedback signal.
Claim 14
Dependent Claim
94 words
The apparatus according to claim 9 , wherein said delay adjustment circuit comprises: an analog loop filter circuit configured to generate one of said one or more first control signals in response to a second control signal and a third control signal; a first phase detector circuit configured to generate said second and third control signals in response to said input signal and said feedback signal; and a second phase detector circuit configured to generate another of said one or more first control signals in response to said input signal and said feedback signal.
Claim 15
Independent Claim
81 words
An apparatus comprising: means for generating an output signal and a plurality of clock signals in response to an input signal and control a plurality of select signals, wherein a phase of said output signal is adjusted in response to one or more control signals; means for generating a said plurality of select signals and a said plurality of clock signals; and means for generating said one or more control signals in response to said input signal and said output signal.
Claim 16
Independent Claim
81 words
An apparatus comprising: means for generating an output signal and a plurality of clock signals in response to an input signal and control a plurality of select signals, wherein a phase of said output signal is adjusted in response to one or more control signals; means for generating a said plurality of select signals and a said plurality of clock signals; and means for generating said one or more control signals in response to said input signal and said output signal.
Claim 17
Independent Claim
114 words
A method for locking and adjusting a phase of an output signal with respect to a phase of an input signal comprising the steps of: (A) generating an output signal and a plurality of phase of an input signal in response to an said input signal and a plurality of select signals, wherein a phase of said output signal is adjusted in response to said one or more control signals; (B) generating said plurality of select signals in response to said one or more control signals and said plurality of phase of said input signal; and (C) generating said one or more control signals in response to said input signal and said output signal.
Claim 18
Independent Claim
114 words
A method for locking and adjusting a phase of an output signal with respect to a phase of an input signal comprising the steps of: (A) generating an output signal and a plurality of phase of an input signal in response to an said input signal and a plurality of select signals, wherein a phase of said output signal is adjusted in response to said one or more control signals; (B) generating said plurality of select signals in response to said one or more control signals and said plurality of phase of said input signal; and (C) generating said one or more control signals in response to said input signal and said output signal.
Claim 19
Dependent Claim
19 words
The method according to claim 15 , wherein said one or more control signals comprises a digital control signal.
Claim 20
Dependent Claim
34 words
The method according to claim 15 , wherein step (B) comprises: updating a plurality of pointers in response to said one or more control signals and said plurality of phases of said input signal.
Claim 21
Dependent Claim
20 words
The method according to claim 15 , wherein said output signal is generated in response to a self-clocking delay line.
Claim 22
Dependent Claim
54 words
The method according to claim 15 , wherein step (A) comprises: controlling a state of a delay element in response to (i) said one or more control signals, (ii) a state of a previous delay element, (iii) a state of a next delay element and (iv) a clock signal generated by said delay element.
Claim 23
Independent Claim
175 words
An apparatus comprising: a delay line configured to generate an output signal in response to an input signal and one or more first control signals, wherein (i) said delay line generates a plurality of select signals in response to said one or more first control signals and a plurality of clock signals and (ii) a phase of said output signal is adjusted in response to said one or more first control signals; an analog loop filter circuit configured to generate one of said one or more first control signals in response to a second control signal and a third control signal; a first phase detector circuit configured to generate said second control signal and said third control signal in response to said input signal and a feedback signal; a second phase detector circuit configured to generate another of said one or more first control signals in response to said input signal and said feedback signal; and a delay circuit configured to generate said feedback signal in response to said output signal and a predetermined delay.
Claim 24
Independent Claim
175 words
An apparatus comprising: a delay line configured to generate an output signal in response to an input signal and one or more first control signals, wherein (i) said delay line generates a plurality of select signals in response to said one or more first control signals and a plurality of clock signals and (ii) a phase of said output signal is adjusted in response to said one or more first control signals; an analog loop filter circuit configured to generate one of said one or more first control signals in response to a second control signal and a third control signal; a first phase detector circuit configured to generate said second control signal and said third control signal in response to said input signal and a feedback signal; a second phase detector circuit configured to generate another of said one or more first control signals in response to said input signal and said feedback signal; and a delay circuit configured to generate said feedback signal in response to said output signal and a predetermined delay.
References Cited (Backward Citations)
US5844954A
Cited
US5923597A
Cited
US6222894B1
Cited
US6144713A
Cited
US6337590B1
Cited
US6087868A
Cited
US5900834A
Cited
US6064232A
Cited
US6125158A
Cited
US5994934A
Cited
US6065126A
Cited
US6069506A
Cited
US6100733A
Cited
US6297680B1
Cited
US6242955B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-05-04 | 2007-11-03 | 2008-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-05-04 | 2011-11-03 | 2012-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-05-04 | 2015-11-03 | 2016-05-04 | $7700.00 | Window Closed / Lapsed |