US6065126A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for executing plurality of operations per clock cycle in a single processing unit with a self-timed and self-enabled distributed clock
Assignee: Janus Semiconductor Research LLC
•
Filing: 1998-02-02
•
Granted: 2000-05-16
•
Expires: 2018-02-02
Abstract
Abstract A self-timed and self-enabled distributed clock is provided for a functional unit that has variable executing time. The self-timed clock provides plurality of clock pulses within a clock cycle for latching of result and starting execution of the next operation. The functional unit can execute more than one operation per clock cycle thus increasing the utilization of the execute unit and the performance of the processor. The state machine is designed to keep track of the current clock pulse and the execution time of the current operation. The functional unit includes the output queue buffer to keep plurality of results from execute unit. The functional unit executes data close to its optimal timing while the data between functional units are synchronized on the clock boundary as in synchronous design. It is more efficient than synchronous design yet the outputs are deterministic as the clocking is preserved in the design.
Inventors
- 👤 Thang Minh Tran
- 👤 Rupaka Mahalingaiah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:54
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F1/00; G06F1/04; G06F1/10; G06F9/3867; G06F9/3871; G06F9/3875
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
173 words
A self-timed and self-enabled clock circuit for synchronizing a plurality of operations in a functional unit, comprising: a control circuit that detects input clock pulses and that provides an enable signal while the input clock pulses are provided; a clock delay device, coupled to the control circuit, that has a plurality of inputs and a plurality of outputs that provide output clock pulses when the clock delay device is enabled, the inputs including: a feedback clock input that is coupled to the output of the clock delay device; a clock input for receiving the input clock pulses; and an enable input that receives the enable signal to enable the clock delay device; and an operation control circuit, coupled to the control circuit and the clock delay device, that has an input indicating execution latency of an operation and a plurality of outputs that schedule the operation in the functional unit; wherein the clock delay device, when enabled by the enable signal, provides output clock pulses that are synchronized with the input clock pulses.
Claim 2
Dependent Claim
173 words
A self-timed and self-enabled clock circuit for synchronizing a plurality of operations in a functional unit, comprising: a control circuit that detects input clock pulses and that provides an enable signal while the input clock pulses are provided; a clock delay device, coupled to the control circuit, that has a plurality of inputs and a plurality of outputs that provide output clock pulses when the clock delay device is enabled, the inputs including: a feedback clock input that is coupled to the output of the clock delay device; a clock input for receiving the input clock pulses; and an enable input that receives the enable signal to enable the clock delay device; and an operation control circuit, coupled to the control circuit and the clock delay device, that has an input indicating execution latency of an operation and a plurality of outputs that schedule the operation in the functional unit; wherein the clock delay device, when enabled by the enable signal, provides output clock pulses that are synchronized with the input clock pulses.
Claim 3
Dependent Claim
23 words
The clock circuit of claim 1 wherein the input clock pulses are provided from an output of another self-timed and self-enabled clock circuit.
Claim 4
Dependent Claim
24 words
The clock circuit of claim 1 further comprising: a pulse shaper circuit, coupled to the clock delay device, that provides the output clock pulses.
Claim 5
Dependent Claim
34 words
The clock circuit of claim 1 further comprising: the control circuit further including a stall input, the control circuit disabling the clock delay device if a stall signal is received at the stall input.
Claim 6
Dependent Claim
19 words
The clock circuit of claim 1 wherein controlling an operation in the functional unit means shifting and latching data.
Claim 7
Dependent Claim
14 words
The clock of claim 1 wherein the operation control circuit is a state machine.
Claim 8
Dependent Claim
50 words
The clock circuit of claim 1 further comprising: the clock delay device including a second clock input; and wherein the clock delay device, when enabled by the enable signal, provides output clock pulses that are synchronized with the input clock pulses and clock signals provided to the second clock input.
Claim 9
Dependent Claim
42 words
The clock circuit of claim 7 further comprising: the input clock pulses being provided from an output of a previous self-timed and self-enabled clock circuit; and the second clock input receiving clock pulses provided from a subsequent self-timed and self-enabled clock circuit.
Claim 10
Dependent Claim
20 words
The clock circuit of claim 1 wherein the clock delay device comprises a plurality of delay blocks sequentially coupled together.
Claim 11
Dependent Claim
38 words
The clock circuit of claim 9 wherein the outputs of the clock delay device are coupled to each of the plurality of delay blocks such that each output clock pulse resets each of the plurality of delay blocks.
Claim 12
Dependent Claim
16 words
The clock circuit of claim 9 wherein each of the delay blocks comprises coupled logic gates.
Claim 13
Dependent Claim
21 words
The clock circuit of claim 9 wherein at least one of the plurality of delay blocks provides an intermediate clock edge.
Claim 14
Dependent Claim
29 words
The clock circuit of claim 12 wherein the intermediate clock edge and the outputs of the operation control circuit are used to schedule an operation in the functional unit.
Claim 15
Dependent Claim
18 words
The clock circuit of claim 9 wherein one of the plurality of delay blocks comprises programmable delay logic.
Claim 16
Dependent Claim
31 words
The clock circuit of claim 14 wherein the programmable delay logic comprises: a plurality of delay devices; and selection logic coupled to select any one of the plurality of delay devices.
Claim 17
Dependent Claim
47 words
The clock circuit of claim 15 further comprising: each of the plurality of delay devices receiving an external clock signal and providing a corresponding clock edge; and the selection logic selecting a delay device providing a clock edge that most closely corresponds with the external clock signal.
Claim 18
Dependent Claim
30 words
The clock circuit of claim 16 wherein the selection logic selects a delay device having a clock edge that occurs closest to a controlling edge of the external clock signal.
Claim 19
Dependent Claim
199 words
A functional block, comprising: an input queue buffer having a data input and an output, the data input being the data input of said functional block; an output queue buffer having a result input and a data output, the data output being the data output of said functional block; an execution unit that has an input coupled to the output of the input queue buffer and a result output coupled to the result input of the output queue buffer; a self clock that has an output, a plurality of output clocks coupled to the input queue buffer and the output queue buffer, a first clock input, a feedback input coupled to the output of the self clock, and an enable input; the self clock, when enabled, providing output clock pulses that are synchronized with clock pulses received at the first clock input; and a control block, coupled to the input queue buffer, the output queue buffer, the execution unit and self clock, that has an enable output coupled to the enable input of the self clock, a plurality of select outputs coupled to the input queue buffer, and a plurality of enable outputs coupled to the output queue buffer.
Claim 20
Dependent Claim
199 words
A functional block, comprising: an input queue buffer having a data input and an output, the data input being the data input of said functional block; an output queue buffer having a result input and a data output, the data output being the data output of said functional block; an execution unit that has an input coupled to the output of the input queue buffer and a result output coupled to the result input of the output queue buffer; a self clock that has an output, a plurality of output clocks coupled to the input queue buffer and the output queue buffer, a first clock input, a feedback input coupled to the output of the self clock, and an enable input; the self clock, when enabled, providing output clock pulses that are synchronized with clock pulses received at the first clock input; and a control block, coupled to the input queue buffer, the output queue buffer, the execution unit and self clock, that has an enable output coupled to the enable input of the self clock, a plurality of select outputs coupled to the input queue buffer, and a plurality of enable outputs coupled to the output queue buffer.
Claim 21
Dependent Claim
34 words
The functional block of claim 18 wherein the input queue buffer including a decode circuit to detect execution latency of an operation and an output from said decode circuit coupled to the control block.
Claim 22
Dependent Claim
33 words
The functional block of claim 18 wherein the execution unit includes a decode circuit to detect execution latency of an operation and an output from said decode circuit coupled to the control block.
Claim 23
Dependent Claim
57 words
The functional block of claim 18 further comprising: the input queue buffer including a first storage device coupled to a second storage device and to the execution unit; and the second storage device shifts its data to the first storage device by the select outputs from the control block and the clock pulses from the self clock.
Claim 24
Dependent Claim
54 words
The functional block of claim 18 further comprising: the output queue buffer including a first storage device coupled to a second storage device and to the execution unit; and the storage devices latch data from the execution unit by the enable outputs from the control block and the clock pulses from the self clock.
Claim 25
Dependent Claim
16 words
The functional block of claim 18 wherein the queue buffer comprises a plurality of storage devices.
Claim 26
Dependent Claim
14 words
The functional block of claim 23 wherein the plurality of storage devices comprise registers.
Claim 27
Independent Claim
104 words
A method of operation of a functional block, comprising: receiving input data and corresponding first input clock pulses; activating a self clock to provide an output clock pulse for each first input clock pulse; detecting execution latency of an operation and generating, by self clock, an output clock pulse according to the execution latency; processing the input data, generating an output result, and using the output clock pulse to latch the output result into output queue buffer; providing an output data from the output queue buffer; and deactivating the self clock while first input clock pulses are not received or during a stall condition.
Claim 28
Independent Claim
104 words
A method of operation of a functional block, comprising: receiving input data and corresponding first input clock pulses; activating a self clock to provide an output clock pulse for each first input clock pulse; detecting execution latency of an operation and generating, by self clock, an output clock pulse according to the execution latency; processing the input data, generating an output result, and using the output clock pulse to latch the output result into output queue buffer; providing an output data from the output queue buffer; and deactivating the self clock while first input clock pulses are not received or during a stall condition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-16 | 2003-11-15 | 2004-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-16 | 2007-11-15 | 2008-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-16 | 2011-11-15 | 2012-05-16 | $7700.00 | Window Closed / Lapsed |