Multilayered doped conductor

Claim 2

A semiconductor device for an integrated circuit having a substrate with a first surface provided with a gate structure formed thereon, source/drain regions of the substrate having a first portion with a first dopant at a first dopant concentration on opposite sides of the gate structure, the device comprising: a conductor provided adjacent the gate structure contacting one of said source/drain regions, said conductor comprising: a first conductive layer having a second dopant at a second dopant concentration; and a second conducive layer having a third dopant at a third dopant concentration formed on said first conductive layer.

Claim 3

The device of claim 1 wherein said second dopant diffusivity is less than said third dopant.

Claim 4

The device of claim 1 wherein said second dopant forms a shallow diffusion region in said one of the source/drain regions beneath said conductor having a dopant concentration greater than said first dopant concentration.

Claim 5

The device of claim 1 wherein said third dopant provides a graded dopant concentration in said one of source/drain regions below and adjacent said shallow diffusion region.

Claim 6

The device of claim 1 , wherein said first dopant is selected from the group consisting of arsenic, antimony, phosphorous, and combination thereof, said second dopant is selected from the group consisting of arsenic and antimony, and said third dopant comprises phosphorus.

Claim 7

The device of claim 1 , wherein said first dopant, said second dopant, and said third dopant each comprises boron, boron bifluoride, borane, or combination thereof.

Claim 8

The device of claim 1 wherein said first dopant concentration, said second dopant concentration, and said third dopant concentration are each from about 1 E 19 ions/cm 3 to about 1 E 21 ions/cm 3 .

Claim 9

The device of claim 3 wherein said shallow diffusion region extends beneath said conductor to a depth of less than about 0.02 μm.

Claim 10

The device of claim 3 wherein said shallow diffusion region is at least partially located beneath a spacer of said gate structure.

Claim 11

The device of claim 1 wherein said conductor is a plug, digitline contact, or both.

Claim 12

The device of claim 1 wherein said conductor is a feature selected from the group consisting of a plug, a capacitor plate, a storage node, a digital line contact, and an active region contact.

Claim 13

The device of claim 1 wherein said first conductive layer comprises a semiconductor or crystalline material.

Claim 14

The device of claim 1 wherein said second conductive layer comprises a semiconductor or crystalline material.

Claim 15

The device of claim 1 wherein said first and second conductive layers are each selected from the group consisting of SiGe, polysilicon, and combinations thereof.

Claim 16

An integrated circuit device having a gate electrode overlying a gate oxide layer on a surface of a semiconductor substrate, an oxide layer lying on a surface and sidewalls of the gate electrode, spacers on sidewalls of said oxide layer, lightly doped source/drain regions lying within the semiconductor substrate on opposite sides of said gate electrode and extending at least partially beneath said sidewalls of said oxide layer forming an overlap region; the device comprising: at least one conductor provided adjacent one of said spacers contacting one of said source/drain regions, said conductor comprising: a first conductive layer having a first dopant at a first dopant concentration; a second conductive layer having a second dopant at a second dopant concentration formed on said first conductive layer, said first dopant having a diffusivity less than said second dopant; a shallow diffusion region of said first dopant in said one of the source/drain regions beneath said conductor; and a graded dopant concentration of said second dopant in said one of the source/drain regions below and adjacent said shallow diffusion region.

Claim 17

An integrated circuit device having a gate electrode overlying a gate oxide layer on a surface of a semiconductor substrate, an oxide layer lying on a surface and sidewalls of the gate electrode, spacers on sidewalls of said oxide layer, lightly doped source/drain regions lying within the semiconductor substrate on opposite sides of said gate electrode and extending at least partially beneath said sidewalls of said oxide layer forming an overlap region; the device comprising: at least one conductor provided adjacent one of said spacers contacting one of said source/drain regions, said conductor comprising: a first conductive layer having a first dopant at a first dopant concentration; a second conductive layer having a second dopant at a second dopant concentration formed on said first conductive layer, said first dopant having a diffusivity less than said second dopant; a shallow diffusion region of said first dopant in said one of the source/drain regions beneath said conductor; and a graded dopant concentration of said second dopant in said one of the source/drain regions below and adjacent said shallow diffusion region.

Claim 18

The device of claim 15 wherein said at least one conductor is a plug, active region contact, or both.

Claim 19

The device of claim 15 wherein said first dopant is selected from the group consisting of arsenic, antimony, and combinations thereof.

Claim 20

The device of claim 15 wherein said second dopant comprises phosphorus.

Claim 21

The device of claim 15 , wherein said first dopant comprises boron, boron bifluoride, borane, or combinations thereof.

Claim 22

The device of claim 15 wherein said second dopant comprises boron, boron bifluoride, borane, or combinations thereof.

Claim 23

The device of claim 15 wherein said first dopant concentration is from about 1 E 19 ions/cm 3 to about 1 E 21 ions/cm 3 .

Claim 24

The device of claim 15 wherein said second dopant concentration is from about 1 E 19 ions/cm 3 to about 1 E 21 ions/cm 3 .

Claim 25

An integrated circuit device comprising: a gate electrode overlying a gate oxide layer on a surface of a semiconductor substrate; an oxide layer lying on a surface and sidewalls of the gate electrode; spacers on sidewalls of said oxide layer; lightly doped source/drain regions lying within the semiconductor substrate on opposite sides of said gate electrode, and extending at least partially beneath said sidewalls of said oxide layer forming an overlap region; pocket implants underlying the lightly doped source/drain regions in the semiconductor substrate; heavily doped source/drain regions lying within the semiconductor substrate adjacent to the lightly doped source/drain regions; and a conductor provided with a first conductive layer on said semiconductor substrate, and a second conductive layer adjacent said first conductive layer, said first conductive layer having a first dopant, said second conductive layer having a second dopant, said first dopant diffusivity is less than said second dopant.

Claim 26

An integrated circuit device comprising: a gate electrode overlying a gate oxide layer on a surface of a semiconductor substrate; an oxide layer lying on a surface and sidewalls of the gate electrode; spacers on sidewalls of said oxide layer; lightly doped source/drain regions lying within the semiconductor substrate on opposite sides of said gate electrode, and extending at least partially beneath said sidewalls of said oxide layer forming an overlap region; pocket implants underlying the lightly doped source/drain regions in the semiconductor substrate; heavily doped source/drain regions lying within the semiconductor substrate adjacent to the lightly doped source/drain regions; and a conductor provided with a first conductive layer on said semiconductor substrate, and a second conductive layer adjacent said first conductive layer, said first conductive layer having a first dopant, said second conductive layer having a second dopant, said first dopant diffusivity is less than said second dopant.

Claim 27

The device of claim 23 further comprising a shallow diffusion region in said one of the lightly doped source/drain regions beneath said conductor, and a graded dopant concentration in said one of the lightly doped source/drain regions below and adjacent said shallow diffusion region.

Claim 28

The device of claim 23 wherein said conductor is adjacent one of said spacers at least partially contacting one of said lightly doped source/drain regions.

Claim 29

The device of claim 23 , wherein said lightly doped source/drain regions and heavily doped source/drain regions each have a dopant selected from the group consisting of arsenic, antimony, phosphorous, and combinations thereof, said first dopant is selected from the group consisting of arsenic, antimony, and combinations thereof, and said second dopant comprises phosphorus.

Claim 30

The device of claim 23 , wherein said lightly doped source/drain regions and heavily doped source/drain regions each have a dopant selected from the group consisting of boron, boron bifluoride, borane, and combinations thereof, said first dopant is selected from the group consisting of boron, boron bifluoride, borane, and combinations thereof, and said second dopant is selected from the group consisting of boron, boron bifluoride, and borane, and combinations thereof.

Claim 31

The device of claim 23 wherein said first and second conductive layers each have a dopant concentration from about 1 E 19 ions/cm 3 to about 1 E 21 ions/cm 3 .

Claim 32

A DRAM device having a buried capacitor memory bit cell including a substrate having a first surface, a gate structure formed on said first surface, said gate structure comprising a wordline, lightly doped source/drain regions formed within said substrate on opposite sides of said gate structure, the DRAM device comprising: a conductor provided adjacent said gate structure contacting one of said lightly doped source/drain regions forming a portion of a storage node, said conductor comprising: a first conductive layer having a first dopant at a first dopant concentration; and a second conductive layer having a second dopant at a second dopant concentration formed on said first conductive layer, said second dopant diffusivity is greater than said first dopant.

Claim 33

A DRAM device having a buried capacitor memory bit cell including a substrate having a first surface, a gate structure formed on said first surface, said gate structure comprising a wordline, lightly doped source/drain regions formed within said substrate on opposite sides of said gate structure, the DRAM device comprising: a conductor provided adjacent said gate structure contacting one of said lightly doped source/drain regions forming a portion of a storage node, said conductor comprising: a first conductive layer having a first dopant at a first dopant concentration; and a second conductive layer having a second dopant at a second dopant concentration formed on said first conductive layer, said second dopant diffusivity is greater than said first dopant.

Claim 34

The DRAM device of claim 29 further comprising a shallow diffusion region in said one of the lightly doped source/drain regions beneath said conductor and having a dopant concentration greater than the lightly doped source/drain regions.

Claim 35

The DRAM device of claim 30 further comprising a graded dopant concentration in said one of lightly doped source/drain regions below and adjacent said shallow diffusion region.

Claim 36

A DRAM device having a buried digitline memory bit cell including a substrate having a first surface, a gate structure formed on said first surface, said gate structure comprising a wordline, lightly doped source/drain regions formed within said substrate on opposite sides of said gate structure, the DRAM device comprising: a conductor provided adjacent said gate structure contacting one of said lightly doped source/drain regions forming a portion of a storage node, said conductor comprising: a first conductive layer having a first dopant at a first dopant concentration; and a second conductive layer having a second dopant at a second dopant concentration formed on said first conductive layer, said second dopant diffusivity is greater than said first dopant.

Claim 37

A DRAM device having a buried digitline memory bit cell including a substrate having a first surface, a gate structure formed on said first surface, said gate structure comprising a wordline, lightly doped source/drain regions formed within said substrate on opposite sides of said gate structure, the DRAM device comprising: a conductor provided adjacent said gate structure contacting one of said lightly doped source/drain regions forming a portion of a storage node, said conductor comprising: a first conductive layer having a first dopant at a first dopant concentration; and a second conductive layer having a second dopant at a second dopant concentration formed on said first conductive layer, said second dopant diffusivity is greater than said first dopant.

Claim 38

The DRAM device of claim 32 further comprising a shallow diffusion region in said one of the lightly doped source/drain regions beneath said conductor having a dopant concentration greater than said lightly doped source/drain regions.

Claim 39

The DRAM device of claim 33 further comprising a graded dopant concentration in said one of lightly doped source/drain regions below and adjacent said shallow diffusion region.

Claim 40

A processor-based system having a processor, and an integrated circuit semiconductor device coupled to said processor, said integrated circuit semiconductor device including a substrate having a first surface, a gate structure formed on said first surface, source/drain regions formed within said substrate on opposite sides of said gate structure, each of the source/drain regions having a first portion with a first dopant at a first dopant concentration, the system comprising: a conductor provided adjacent said gate structure contacting one of said source/drain regions, said conductor comprising: a first conductive layer having a second dopant at a second dopant concentration; a second conductive layer having a third dopant at a third dopant concentration formed on said first conductive layer, said second dopant having a diffusivity less than said third dopant; a shallow diffusion region in said one of the source/drain regions beneath said conductor having a dopant concentration of said second dopant greater than said first dopant concentration; and a graded dopant concentration of said third dopant in said one of source/drain regions below and adjacent said shallow diffusion region.

Claim 41

A processor-based system having a processor, and an integrated circuit semiconductor device coupled to said processor, said integrated circuit semiconductor device including a substrate having a first surface, a gate structure formed on said first surface, source/drain regions formed within said substrate on opposite sides of said gate structure, each of the source/drain regions having a first portion with a first dopant at a first dopant concentration, the system comprising: a conductor provided adjacent said gate structure contacting one of said source/drain regions, said conductor comprising: a first conductive layer having a second dopant at a second dopant concentration; a second conductive layer having a third dopant at a third dopant concentration formed on said first conductive layer, said second dopant having a diffusivity less than said third dopant; a shallow diffusion region in said one of the source/drain regions beneath said conductor having a dopant concentration of said second dopant greater than said first dopant concentration; and a graded dopant concentration of said third dopant in said one of source/drain regions below and adjacent said shallow diffusion region.