Reduced parasitic leakage in semiconductor devices

Claim 1

A method of fabricating a semiconductor memory comprises the steps of: providing a substrate with a trench; forming a capacitor in the trench, the capacitor including a dielectric collar formed within a collar region adjacent to the trench, a buried diffusion region surrounding a lower portion of the trench and a node formed within the trench; forming a transistor having a gate, a first diffusion region and a second diffusion region in the substrate, one of the first and second diffusion regions being coupled to the node by a node diffusion; and forming a third diffusion region in the substrate extending laterally outward from within the trench and disposed adjacent to the collar by doping the collar region with dopants having a conductivity opposite of the buried diffusion region and the node diffusion, wherein the dopants include Boron having a concentration of between about 5×10 17 to 2×10 18 cm -3 , the third diffusion region comprising a dopant concentration sufficient to increase a gate threshold voltage of a parasitic transistor formed between the buried diffusion region and the node diffusion, so as to reduce leakage.

Claim 2

A method of fabricating a semiconductor memory comprises the steps of: providing a substrate with a trench; forming a capacitor in the trench, the capacitor including a dielectric collar formed within a collar region adjacent to the trench, a buried diffusion region surrounding a lower portion of the trench and a node formed within the trench; forming a transistor having a gate, a first diffusion region and a second diffusion region in the substrate, one of the first and second diffusion regions being coupled to the node by a node diffusion; and forming a third diffusion region in the substrate extending laterally outward from within the trench and disposed adjacent to the collar by doping the collar region with dopants having a conductivity opposite of the buried diffusion region and the node diffusion, wherein the dopants include Boron having a concentration of between about 5×10 17 to 2×10 18 cm -3 , the third diffusion region comprising a dopant concentration sufficient to increase a gate threshold voltage of a parasitic transistor formed between the buried diffusion region and the node diffusion, so as to reduce leakage.

Claim 6

A method of fabricating a semiconductor memory comprises the steps of: providing a substrate having a pad stack formed thereon; etching an opening through the pad stack; doping the substrate such that a peak concentration is located within a collar region located within the substrate, implanting the dopants at an energy between about 200 keV to about 350 keV at a dose of between about 1.5×10 13 cm -2 to about 3.5×10 13 cm -2 ; annealing the substrate to diffuse the dopants laterally outward from the collar region to form a third diffusion region; etching a trench through the collar region of the substrate; removing the pad stack; forming a capacitor in the trench, the capacitor including a collar formed within the collar region adjacent to the trench, a buried diffusion region surrounding a lower portion of the trench and a node within the trench; forming a transistor having a gate, a first diffusion region and a second diffusion region in the substrate, one of the first and second diffusion regions being coupled to the node by a node diffusion; reducing leakage from a parasitic transistor by providing the third diffusion region which comprises a dopant concentration sufficient to increase a gate threshold voltage of the parasitic transistor formed between the buried diffusion region and the node diffusion.

Claim 7

A method of fabricating a semiconductor memory comprises the steps of: providing a substrate having a pad stack formed thereon; etching an opening through the pad stack; doping the substrate such that a peak concentration is located within a collar region located within the substrate, implanting the dopants at an energy between about 200 keV to about 350 keV at a dose of between about 1.5×10 13 cm -2 to about 3.5×10 13 cm -2 ; annealing the substrate to diffuse the dopants laterally outward from the collar region to form a third diffusion region; etching a trench through the collar region of the substrate; removing the pad stack; forming a capacitor in the trench, the capacitor including a collar formed within the collar region adjacent to the trench, a buried diffusion region surrounding a lower portion of the trench and a node within the trench; forming a transistor having a gate, a first diffusion region and a second diffusion region in the substrate, one of the first and second diffusion regions being coupled to the node by a node diffusion; reducing leakage from a parasitic transistor by providing the third diffusion region which comprises a dopant concentration sufficient to increase a gate threshold voltage of the parasitic transistor formed between the buried diffusion region and the node diffusion.