Patent US6617639B1 successfully refreshed from Google Patents.
US6617639B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling
Assignee: Monterey Research LLC
•
Filing: 2002-06-21
•
Granted: 2003-09-09
•
Expires: 2022-06-21
Abstract
Abstract A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, in which the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material.
Inventors
- 👤 Zhigang Wang
- 👤 Xin Guo
- 👤 Yue-Song He
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:52
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/691; H10D64/693
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
199 words
A floating gate flash memory device comprising: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer, and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein the tunnel dielectric material layer comprises a first high-K dielectric material, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprises an additional high-K dielectric material, and at least one of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprises a composite dielectric material including elements of the first or additional high-K dielectric material and at least one additional dielectric material.
Claim 2
Dependent Claim
199 words
A floating gate flash memory device comprising: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer, and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein the tunnel dielectric material layer comprises a first high-K dielectric material, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprises an additional high-K dielectric material, and at least one of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprises a composite dielectric material including elements of the first or additional high-K dielectric material and at least one additional dielectric material.
Claim 3
Dependent Claim
166 words
The floating gate flash memory device of claim 1 , wherein the first high-K dielectric material and the additional high-K dielectric material independently comprise at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), barium titanate (BaTiO 3 ), titanium dioxide (TiO 2 ), cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), lead titanate (PbTiO 3 ), strontium titanate (SrTiO 3 ), lead zirconate (PbZrO 3 ), tungsten oxide (WO 3 ), yttrium oxide (Y 2 O 3 ), bismuth silicon oxide (Bi 4 Si 2 O 12 ), barium strontium titanate (BST) (Ba 1−x Sr x TiO 3 ), PMN (PbMg x Nb 1−x O 3 ), PZT (PbZr x Ti 1−x O 3 ), PZN (PbZn x Nb 1−x O 3 ), and PST (PbSc x Ta 1−x O 3 ), lead lanthanum titanate, strontium bismuth tantalate, bismuth titanate and barium zirconium titanate.
Claim 4
Dependent Claim
54 words
The floating gate flash memory device of claim 1 , wherein at least two of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprise a composite dielectric material including elements of the respective first or additional high-K dielectric material and at least one additional dielectric material.
Claim 5
Dependent Claim
23 words
The floating gate flash memory device of claim 1 , wherein the floating gate electrode comprises at least one of polysilicon or polysilicon-germanium.
Claim 6
Dependent Claim
28 words
The floating gate flash memory device of claim 1 , wherein the control gate electrode comprises at least one of polysilicon, polysilicon-germanium, a metal silicide or a metal.
Claim 7
Dependent Claim
23 words
The floating gate flash memory device of claim 1 , wherein the layer comprising a nitride comprises silicon nitride or silicon-rich silicon nitride.
Claim 8
Dependent Claim
35 words
The floating gate flash memory device of claim 1 , wherein both the bottom dielectric material layer comprises a second high-K dielectric material and the top dielectric material layer comprises a third high-K dielectric material.
Claim 9
Dependent Claim
157 words
A floating gate flash memory device comprising: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material, further comprising at least one interfacial barrier layer.
Claim 10
Dependent Claim
157 words
A floating gate flash memory device comprising: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material, further comprising at least one interfacial barrier layer.
Claim 11
Dependent Claim
202 words
A floating gate flash memory device comprising: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising silicon nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein the tunnel dielectric material layer comprises a first high-K dielectric material, the bottom dielectric material layer comprises a second high-K dielectric material, and the top dielectric material layer comprises a third high-K dielectric material, wherein at least one of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprises a composite dielectric material including elements of the respective first, second or third high-K dielectric material and at least one additional dielectric material.
Claim 12
Dependent Claim
202 words
A floating gate flash memory device comprising: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising silicon nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein the tunnel dielectric material layer comprises a first high-K dielectric material, the bottom dielectric material layer comprises a second high-K dielectric material, and the top dielectric material layer comprises a third high-K dielectric material, wherein at least one of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprises a composite dielectric material including elements of the respective first, second or third high-K dielectric material and at least one additional dielectric material.
Claim 13
Dependent Claim
159 words
The floating gate flash memory device of claim 9 , wherein each high-K dielectric material independently comprises at least one of hafnium oxide (HFO 2 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), barium titanate (BaTiO 3 ), titanium dioxide (TiO 2 ), cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), lead titanate (PbTiO 3 ), strontium titanate (SrTiO 3 ), lead zirconate (PbZrO 3 ), tungsten oxide (WO 3 ), yttrium oxide (Y 2 O 3 ), bismuth silicon oxide (Bi 4 Si 2 O 12 ), barium strontium titanate (BST) (Ba 1−x Sr x TiO 3 ), PMN (PbMg x Nb 1−x O 3 ), PZT (PbZr x Ti 1−x O 3 ), PZN (PbZn x Nb 1−x O 3 ), and PST (PbSc x Ta 1−x O 3 ), lead lanthanum titanate, strontium bismuth tantalate, bismuth titanate and barium zirconium titanate.
Claim 14
Dependent Claim
55 words
The floating gate flash memory device of claim 9 , wherein at least two of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprise a composite dielectric material including elements of the respective first, second or third high-K dielectric material and at least one additional dielectric material.
Claim 15
Dependent Claim
28 words
The floating gate flash memory device of claim 8 , wherein the at least one interfacial barrier layer is on an upper surface of the floating gate electrode.
Claim 16
Dependent Claim
27 words
The floating gate flash memory device of claim 8 , wherein the at least one interfacial barrier layer is on an upper surface of the semiconductor substrate.
Claim 17
Dependent Claim
52 words
The floating gate flash memory device of claim 1 , wherein each of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprise a composite dielectric material including elements of the respective first or additional high-K dielectric material and at least one additional dielectric material.
Claim 18
Dependent Claim
18 words
The floating gate flash memory device of claim 9 , further comprising at least one interfacial barrier layer.
Claim 19
Dependent Claim
28 words
The floating gate flash memory device of claim 15 , wherein the at least one interfacial barrier layer is on an upper surface of the floating gate electrode.
Claim 20
Dependent Claim
27 words
The floating gate flash memory device of claim 15 , wherein the at least one interfacial barrier layer is on an upper surface of the semiconductor substrate.
Claim 21
Dependent Claim
53 words
The floating gate flash memory device of claim 9 , wherein each of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprise a composite dielectric material including elements of the respective first, second or third high-K dielectric material and at least one additional dielectric material.
Claim 22
Dependent Claim
186 words
A floating gate flash memory device comprising: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer, and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising silicon nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein each of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprises a high-K dielectric material, and at least two of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprise a composite dielectric material including elements of the high-K dielectric material and at least one additional dielectric material.
Claim 23
Dependent Claim
186 words
A floating gate flash memory device comprising: a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer, and c) a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising silicon nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein each of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprises a high-K dielectric material, and at least two of the tunnel dielectric material layer, the bottom dielectric material layer and the top dielectric material layer comprise a composite dielectric material including elements of the high-K dielectric material and at least one additional dielectric material.
Claim 24
Dependent Claim
18 words
The floating gate flash memory device of claim 19 , further comprising at least one interfacial barrier layer.
References Cited (Backward Citations)
US5120672A
Cited
US6013553A
Cited
US6008091A
Cited
US6163049A
Cited
US6309927B1
Cited
US6171900B1
Cited
US6242306B1
Cited
US6438030B1
Cited
US20020142624A1
Cited
US20020115252A1
Cited
US20020106536A1
Cited
US20020190311A1
Cited
US6461905B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-09-08 | 2007-03-10 | 2007-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-09-08 | 2011-03-10 | 2011-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-09-08 | 2015-03-10 | 2015-09-09 | $7700.00 | Window Closed / Lapsed |