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US6586797B2
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Graded composition gate insulators to reduce tunneling barriers in flash memory devices
Assignee: Micron Technology Inc
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Filing: 2001-08-30
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Granted: 2003-07-01
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Expires: 2021-08-30
Abstract
Abstract Flash memory cells are provided that include a first source/drain region and a second source/drain region separated by a channel region. A first gate opposes. A first gate insulator separates the first gate from the channel. The first gate insulator includes a graded composition gate insulator. A second gate is separated from the first gate insulator by a second gate insulator. The above memory cells produce gate insulators with less charging at the interface between composite insulator layers and provide gate insulators with low surface state densities. The memory cells substantially reduce large barrier heights or energy problems by using dielectrics having suitably, adjustably lower barrier heights in contact with the polysilicon floating gate. Such adjustable barrier heights of controlled thicknesses can be formed using a silicon suboxide and a silicon oxycarbide dielectrics prepared according to the process as described herein.
Inventors
- 👤 Leonard Forbes
- 👤 Jerome M. Eldridge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:38
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
78 words
A flash memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator separating the first gate from the channel, wherein the gate insulator includes a graded composition gate insulator, and wherein the first gate insulator provides an electron barrier height between 0.4 eV to 3.2 eV; and a second gate separated from the first gate insulator by a second gate insulator.
Claim 2
Dependent Claim
78 words
A flash memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator separating the first gate from the channel, wherein the gate insulator includes a graded composition gate insulator, and wherein the first gate insulator provides an electron barrier height between 0.4 eV to 3.2 eV; and a second gate separated from the first gate insulator by a second gate insulator.
Claim 3
Dependent Claim
71 words
The flash memory cell of claim 1 , wherein the first gate includes a floating gate and the first gate insulator includes a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity dielectric material with a range between 0.6 eV and 3.2 eV having a silicon suboxide (SiO x with 1<x<2) layer in combination with a SiO 2 layer to form the graded composition gate insulator.
Claim 4
Dependent Claim
143 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator separating the first gate from the channel, wherein the gate insulator includes a graded composition gate insulator; a second gate separated from the first gate insulator by a second gate insulator; and wherein the first gate includes a floating gate and the first gate insulator includes a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity dielectric material with a range between 0.6 eV and 3.2 eV having a silicon suboxide (SiO x with 1<x<2) layer in combination with a SiO 2 layer to form the graded composition gate insulator, and wherein the silicon suboxide layer is formed on top of the SiO 2 layer under the floating gate.
Claim 5
Dependent Claim
143 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator separating the first gate from the channel, wherein the gate insulator includes a graded composition gate insulator; a second gate separated from the first gate insulator by a second gate insulator; and wherein the first gate includes a floating gate and the first gate insulator includes a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity dielectric material with a range between 0.6 eV and 3.2 eV having a silicon suboxide (SiO x with 1<x<2) layer in combination with a SiO 2 layer to form the graded composition gate insulator, and wherein the silicon suboxide layer is formed on top of the SiO 2 layer under the floating gate.
Claim 6
Dependent Claim
67 words
The flash memory cell of claim 1 , wherein the first gate includes a floating gate and the first gate insulator includes a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity dielectric material with a range between 0.6 eV and 3.2 eV having a silicon oxycarbide layer in combination with a silicon suboxide layer to form the graded composition gate insulator.
Claim 7
Dependent Claim
139 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator separating the first gate from the channel, wherein the gate insulator includes a graded composition gate insulator; a second gate separated from the first gate insulator by a second gate insulator; and wherein the first gate includes a floating gate and the first gate insulator includes a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity dielectric material with a range between 0.6 eV and 3.2 eV having a silicon oxycarbide layer in combination with a silicon suboxide layer to form the graded composition gate insulator, and wherein the silicon oxycarbide layer is formed on top of the silicon suboxide layer under the floating gate.
Claim 8
Dependent Claim
139 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator separating the first gate from the channel, wherein the gate insulator includes a graded composition gate insulator; a second gate separated from the first gate insulator by a second gate insulator; and wherein the first gate includes a floating gate and the first gate insulator includes a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity dielectric material with a range between 0.6 eV and 3.2 eV having a silicon oxycarbide layer in combination with a silicon suboxide layer to form the graded composition gate insulator, and wherein the silicon oxycarbide layer is formed on top of the silicon suboxide layer under the floating gate.
Claim 9
Dependent Claim
103 words
A flash memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator having two layers separating the first gate from the channel, wherein a first layer and a second layer of the first gate insulator have a similar dielectric constant to keep the electric fields comparable in each layer, and wherein the first gate insulator provides a low electron barrier height ranging from 0.4 eV to 3.2 eV for charge injection; and a second gate separated from the first gate insulator by a second gate insulator.
Claim 10
Dependent Claim
103 words
A flash memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator having two layers separating the first gate from the channel, wherein a first layer and a second layer of the first gate insulator have a similar dielectric constant to keep the electric fields comparable in each layer, and wherein the first gate insulator provides a low electron barrier height ranging from 0.4 eV to 3.2 eV for charge injection; and a second gate separated from the first gate insulator by a second gate insulator.
Claim 11
Dependent Claim
39 words
The flash memory cell of claim 6 , wherein the first gate includes a floating gate, and wherein the first layer includes a SiO 2 layer and the second layer includes a silicon suboxide (SiO x with 1<x<2) layer.
Claim 12
Dependent Claim
121 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator having two layers separating the first gate from the channel, wherein a first layer and a second layer of the first gate insulator have a similar dielectric constant to keep the electric fields comparable in each layer, and wherein the first gate insulator provides a low electron barrier height ranging from 0.4 eV to 3.2 eV for charge injection; a second gate separated from the first gate insulator by a second gate insulator; and wherein the silicon suboxide layer is formed on top of the SiO 2 layer under the floating gate.
Claim 13
Dependent Claim
121 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator having two layers separating the first gate from the channel, wherein a first layer and a second layer of the first gate insulator have a similar dielectric constant to keep the electric fields comparable in each layer, and wherein the first gate insulator provides a low electron barrier height ranging from 0.4 eV to 3.2 eV for charge injection; a second gate separated from the first gate insulator by a second gate insulator; and wherein the silicon suboxide layer is formed on top of the SiO 2 layer under the floating gate.
Claim 14
Dependent Claim
35 words
The flash memory cell of claim 6 , wherein the first gate includes a floating gate, and wherein the first layer includes a silicon suboxide layer and the second layer includes a silicon oxycarbide layer.
Claim 15
Dependent Claim
149 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator having two layers separating the first gate from the channel, wherein a first layer and a second layer of the first gate insulator have a similar dielectric constant to keep the electric fields comparable in each layer, and wherein the first gate insulator provides a low electron barrier height ranging from 0.4 eV to 3.2 eV for charge injection; a second gate separated from the first gate insulator by a second gate insulator; and wherein the first gate includes a floating gate, and wherein the first layer includes a silicon suboxide layer and the second layer includes a silicon oxycarbide layer, and wherein the silicon oxycarbide layer is formed on top of the silicon suboxide layer under the floating gate.
Claim 16
Dependent Claim
149 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator having two layers separating the first gate from the channel, wherein a first layer and a second layer of the first gate insulator have a similar dielectric constant to keep the electric fields comparable in each layer, and wherein the first gate insulator provides a low electron barrier height ranging from 0.4 eV to 3.2 eV for charge injection; a second gate separated from the first gate insulator by a second gate insulator; and wherein the first gate includes a floating gate, and wherein the first layer includes a silicon suboxide layer and the second layer includes a silicon oxycarbide layer, and wherein the silicon oxycarbide layer is formed on top of the silicon suboxide layer under the floating gate.
Claim 17
Dependent Claim
120 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator having two layers separating the first gate from the channel, wherein a first layer and a second layer of the first gate insulator have a similar dielectric constant to keep the electric fields comparable in each layer, and wherein the first gate insulator provides a low electron barrier height ranging for charge injection; a second gate separated from the first gate insulator by a second gate insulator; and wherein the low electron barrier height of the first gate insulator includes an electron barrier height ranging from 0.4 eV to 3.2 eV.
Claim 18
Dependent Claim
120 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a first gate opposing the channel; a first gate insulator having two layers separating the first gate from the channel, wherein a first layer and a second layer of the first gate insulator have a similar dielectric constant to keep the electric fields comparable in each layer, and wherein the first gate insulator provides a low electron barrier height ranging for charge injection; a second gate separated from the first gate insulator by a second gate insulator; and wherein the low electron barrier height of the first gate insulator includes an electron barrier height ranging from 0.4 eV to 3.2 eV.
Claim 19
Dependent Claim
16 words
The flash memory cell of claim 6 , wherein the second gate includes a control gate.
Claim 20
Dependent Claim
120 words
A flash memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon suboxide (SiO x with 1<x<2) layer in combination with a SiO 2 layer to form the graded composition gate insulator; and a control gate separated from the floating gate insulator by a second gate insulator.
Claim 21
Dependent Claim
120 words
A flash memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon suboxide (SiO x with 1<x<2) layer in combination with a SiO 2 layer to form the graded composition gate insulator; and a control gate separated from the floating gate insulator by a second gate insulator.
Claim 22
Dependent Claim
139 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon suboxide (SiO x with 1<x<2) layer in combination with a SiO 2 layer to form the graded composition gate insulator; and a control gate separated from the floating gate insulator by a second gate insulator; and wherein the silicon suboxide layer is formed on top of the SiO 2 layer under the floating gate.
Claim 23
Dependent Claim
139 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon suboxide (SiO x with 1<x<2) layer in combination with a SiO 2 layer to form the graded composition gate insulator; and a control gate separated from the floating gate insulator by a second gate insulator; and wherein the silicon suboxide layer is formed on top of the SiO 2 layer under the floating gate.
Claim 24
Dependent Claim
29 words
The flash memory cell of claim 13 , wherein the graded composition gate insulator provides a low electron barrier height between 0.4 eV to 3.2 eV for charge injection.
Claim 25
Dependent Claim
144 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon suboxide (SiO x with 1<x<2) layer in combination with a SiO 2 layer to form the graded composition gate insulator; a control gate separated from the floating gate insulator by a second gate insulator; and wherein the low electron barrier height of the graded composition gate insulator includes an electron barrier height ranging from 0.6 eV to 3.2 eV.
Claim 26
Dependent Claim
144 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon suboxide (SiO x with 1<x<2) layer in combination with a SiO 2 layer to form the graded composition gate insulator; a control gate separated from the floating gate insulator by a second gate insulator; and wherein the low electron barrier height of the graded composition gate insulator includes an electron barrier height ranging from 0.6 eV to 3.2 eV.
Claim 27
Dependent Claim
123 words
A flash memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon oxycarbide [(Si x C y O z ] layer in combination with a SiO 2 layer to form the graded composition gate insulator; and a control gate separated from the floating gate insulator by a second gate insulator.
Claim 28
Dependent Claim
123 words
A flash memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon oxycarbide [(Si x C y O z ] layer in combination with a SiO 2 layer to form the graded composition gate insulator; and a control gate separated from the floating gate insulator by a second gate insulator.
Claim 29
Dependent Claim
134 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon oxycarbide layer in combination with a SiO 2 layer to form the graded composition gate insulator; a control gate separated from the floating gate insulator by a second gate insulator; and wherein the silicon oxycarbide layer is formed on top of the SiO 2 layer under the floating gate.
Claim 30
Dependent Claim
134 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon oxycarbide layer in combination with a SiO 2 layer to form the graded composition gate insulator; a control gate separated from the floating gate insulator by a second gate insulator; and wherein the silicon oxycarbide layer is formed on top of the SiO 2 layer under the floating gate.
Claim 31
Dependent Claim
29 words
The flash memory cell of claim 17 , wherein the graded composition gate insulator provides a low electron barrier height between 0.6 eV to 3.2 eV for charge injection.
Claim 32
Dependent Claim
140 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon oxycarbide layer in combination with a SiO 2 layer to form the graded composition gate insulator; a control gate separated from the floating gate insulator by a second gate insulator; and wherein the low electron barrier height of the graded composition gate insulator includes an electron barrier height ranging from 0.4 eV to 3.2 eV.
Claim 33
Dependent Claim
140 words
A flash memory cell comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of approximately 3.2 eV to 3.5 eV and large electron affinity with a range between 0.6 eV to 3.2 eV, and wherein the graded composition gate insulator includes a dielectric material having a silicon oxycarbide layer in combination with a SiO 2 layer to form the graded composition gate insulator; a control gate separated from the floating gate insulator by a second gate insulator; and wherein the low electron barrier height of the graded composition gate insulator includes an electron barrier height ranging from 0.4 eV to 3.2 eV.
Claim 34
Dependent Claim
81 words
A flash memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of 3.0 to 3.2 eV and a large electron affinity of 3.5 to 3.7 eV; and a control gate separated from the floating gate insulator by a second gate insulator.
Claim 35
Dependent Claim
81 words
A flash memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel; a first gate insulator separating the floating gate from the channel, wherein the gate insulator includes a graded composition gate insulator having a low band gap of 3.0 to 3.2 eV and a large electron affinity of 3.5 to 3.7 eV; and a control gate separated from the floating gate insulator by a second gate insulator.
Claim 36
Dependent Claim
29 words
The flash memory cell of claim 21 , wherein the graded composition gate insulator provides a low electron barrier height between 0.4 eV to 3.2 eV for charge injection.
Claim 37
Dependent Claim
32 words
The flash memory cell of claim 22 , wherein the low electron barrier height of the graded composition gate insulator includes an electron barrier height ranging from 0.4 eV to 3.2 eV.
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