Hardware and software co-simulation including executing an analyzed user program

Claim 3

The method according to claim 1 , wherein the analyzed version of the user program is obtained by an analysis process including decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing and pipeline effects.

Claim 4

The method according to claim 1 , wherein one of the significant events is a particular event requiring the user program to interact with the hardware simulator, and wherein the communication is information associated with the particular event, the associated event passed to the hardware simulator.

Claim 5

The method according to claim 3 , further comprising: (d) receiving and processing the associated event information at the processor simulator.

Claim 6

The method according to claim 4 , wherein the associated event information includes time delay information indicating an amount of simulated time since a previous significant event, and wherein said step (d) of processing executes an appropriate amount of hardware simulation time.

Claim 7

The method according to claim 5 , further comprising: (e) suspending step (a) of simulating execution of the user program while the associated event information is processed in said step (d).

Claim 8

The method according to claim 5 , wherein said associated event processing step (d) produces an event result.

Claim 9

The method according to claim 6 , wherein said associated event processing step (d) produces an event result, the method further including: (f) resuming said execution user program simulating step (a) when the event result is produced.

Claim 10

The method according to claim 8 , wherein the event result is an asynchronous event, and wherein said resuming step (f) causes simulation of execution of an asynchronous event handler, the handler being part of the user program.

Claim 11

The method according to claim 9 , wherein the asynchronous event occurs before the processor simulator executes the appropriate amount of hardware simulation time.

Claim 12

The method according to claim 10 , wherein simulating the handler execution accumulates a handler delay time, the method further comprising examining the user program to ensure that the interrupt handler part of the user program does not share variables with any other part of the user program; completing processing of the appropriate amount of time on the hardware simulator, processing a further amount of simulation time corresponding to the handler delay time on the hardware processor.

Claim 13

The method according to claim 9 , further including avoiding the asynchronous event occurring before the processor simulator executes the appropriate amount of hardware simulation time.

Claim 14

The method according to claim 2 , further including: (d) modeling one or more aspects of the target processor execution at a user selected level of detail.

Claim 15

The method according to claim 13 , wherein the analyzing step further comprises: inserting code into the user program that causes at run time the one or more aspects of the target processor execution to be simulated at the selected level of accuracy.

Claim 16

The method according to claim 13 , wherein the one or more aspects are modeled in hardware, and wherein the inserted code causes the one or more aspects to be simulated on the hardware simulator.

Claim 17

The method according to claim 2 , wherein the analyzing step further comprises: inserting code into the user program for detecting execution exceptions at execution time.

Claim 18

A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor having a pipeline, and a user program to be executed on the target processor, the design system comprising: a carrier medium carrying one or more computer readable code segments including: a first set of one or more computer readable code segments to instruct one or more host processors of the host computer system to simulate execution of the user program on the target processor, the simulation including executing an analyzed version of the user program on the one or more host processors; a second set of one or more computer readable code segments to instruct one or more host processors of the host computer system to simulate the target digital circuitry; and a third set of one or more computer readable code segments to instruct the one or more host processors to couple the first set of code segments with the second set of code segments, wherein the first set of code segments includes one or more code segments that cause communication with the second set of code segments using the third set of code segments when an event requires interaction of the user program with the target digital circuitry, wherein the analyzed version of the user program is obtained by decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing and pipeline effects, such that executing the analyzed version of the user program produces timing information incorporating target processor instruction timing and pipeline effects.

Claim 19

A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor having a pipeline, and a user program to be executed on the target processor, the design system comprising: a carrier medium carrying one or more computer readable code segments including: a first set of one or more computer readable code segments to instruct one or more host processors of the host computer system to simulate execution of the user program on the target processor, the simulation including executing an analyzed version of the user program on the one or more host processors; a second set of one or more computer readable code segments to instruct one or more host processors of the host computer system to simulate the target digital circuitry; and a third set of one or more computer readable code segments to instruct the one or more host processors to couple the first set of code segments with the second set of code segments, wherein the first set of code segments includes one or more code segments that cause communication with the second set of code segments using the third set of code segments when an event requires interaction of the user program with the target digital circuitry, wherein the analyzed version of the user program is obtained by decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing and pipeline effects, such that executing the analyzed version of the user program produces timing information incorporating target processor instruction timing and pipeline effects.

Claim 20

A carrier medium carrying computer readable code segments to instruct one or more host processors of a host computer system to simulat e an electronic system that includes target digital circuitry and a target processor having a pipeline, the carrier medium comprising: one or more code segments to instruct the one or more host processors to simulate a user program executing on the target processor, the code segments including one or more code segments to execute an analyzed version of the user program on the one or more host processors, the executing of the analyzed version including accumulating timing information according to the target processor characteristics, the timing information including instruction timing and pipeline effects; one or more code segments to instruct the one or more host processors to simulate the target digital circuitry on a hardware simulator operating on the host computer system, the simulating of the target digital circuitry including accumulating timing information; and one or more code segments to instruct the one or more host processors to pass communication between the simulated target processor and the hardware simulator at significant events, including events that require interaction between the user program and the target digital circuitry.

Claim 21

A carrier medium carrying computer readable code segments to instruct one or more host processors of a host computer system to simulat e an electronic system that includes target digital circuitry and a target processor having a pipeline, the carrier medium comprising: one or more code segments to instruct the one or more host processors to simulate a user program executing on the target processor, the code segments including one or more code segments to execute an analyzed version of the user program on the one or more host processors, the executing of the analyzed version including accumulating timing information according to the target processor characteristics, the timing information including instruction timing and pipeline effects; one or more code segments to instruct the one or more host processors to simulate the target digital circuitry on a hardware simulator operating on the host computer system, the simulating of the target digital circuitry including accumulating timing information; and one or more code segments to instruct the one or more host processors to pass communication between the simulated target processor and the hardware simulator at significant events, including events that require interaction between the user program and the target digital circuitry.

Claim 22

A carrier medium carrying computer readable code segments to instruct one or more processors to simulate on a host computer system the execution of a user program on a target processor having a pipeline, the target processor being part of an electronic system that includes target digital circuitry, the carrier medium comprising: (a) one or more code segments to instruct one or more processors to decompose the user program into linear blocks; (b) one or more code segments to instruct one or more processors to determine linear block timing information including the time delays that would be incurred executing each linear block of the user program on the target processor, the determining using characteristics of the target processor including instruction timing and pipeline characteristics, the block timing information taking into account instruction timing and pipeline effects; (c) one or more code segments to instruct one or more processors to combine the linear block timing information with the user program; (d) one or more code segments to instruct one or more processors of the host computer system to execute the combined user program and linear block timing information on the host computer system; and (e) one or more code segments to instruct one or more processors of the host computer system to simulate the target digital circuitry on a hardware simulator running on the host computer system, wherein execution of the combined user program and linear block timing information on the host computer system includes communicating with the hardware simulator when an event requires interaction of the user program with the target digital circuitry, such that the execution of the combined user program and linear block timing information on the host computer system simulates the execution of the user program on the target processor including providing execution timing that takes into account instruction timing and pipeline effects.

Claim 23

A carrier medium carrying computer readable code segments to instruct one or more processors to simulate on a host computer system the execution of a user program on a target processor having a pipeline, the target processor being part of an electronic system that includes target digital circuitry, the carrier medium comprising: (a) one or more code segments to instruct one or more processors to decompose the user program into linear blocks; (b) one or more code segments to instruct one or more processors to determine linear block timing information including the time delays that would be incurred executing each linear block of the user program on the target processor, the determining using characteristics of the target processor including instruction timing and pipeline characteristics, the block timing information taking into account instruction timing and pipeline effects; (c) one or more code segments to instruct one or more processors to combine the linear block timing information with the user program; (d) one or more code segments to instruct one or more processors of the host computer system to execute the combined user program and linear block timing information on the host computer system; and (e) one or more code segments to instruct one or more processors of the host computer system to simulate the target digital circuitry on a hardware simulator running on the host computer system, wherein execution of the combined user program and linear block timing information on the host computer system includes communicating with the hardware simulator when an event requires interaction of the user program with the target digital circuitry, such that the execution of the combined user program and linear block timing information on the host computer system simulates the execution of the user program on the target processor including providing execution timing that takes into account instruction timing and pipeline effects.