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US5886899A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for analyzing the performance of a microprocessor

Assignee: GlobalFoundries Inc
•
Filing: 1996-01-26
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Granted: 1999-03-23
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Expires: 2016-01-26
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Abstract

Abstract A method for analyzing the performance of a logic circuit driven by a clock signal, such as a microprocessor, identifies a number of operations of interest in a logic circuit and represents the presence of each of such operations by a different symbol. One or more of these symbols are output for perusal at the end of each clock period of operation. In one embodiment, this method is applied to a register transfer level (RTL) simulation of an execution unit of a microprocessor. In that embodiment, the execution sequence of multiple instructions executing simultaneously in the execution unit was analyzed. Because each output symbol represents a summary of a large number of activities that occur in a single clock period of operation or simulation of a complex logic circuit, these symbols can be tabulated in a format that allows a designer of the complex logic circuit to easily spot an unexpected pattern of operation, or an error condition.

Inventors

  • 👤 Warren G. Stapleton

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 08:59
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/3003; G06F11/3024; G06F11/3055; G06F11/32; G06F11/324; G06F11/34; G06F11/3404; G06F11/3466; G06F11/3457

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 135 words
A method for analyzing the performance of a logic circuit driven by a clock signal, comprising the steps of: identifying a number of operations of interest in said logic circuit, said logic circuit being an execution unit of a microprocessor; for each of said operations, creating in an operative model of said logic circuit a status signal, said status signal, when asserted, being representative of a status of said operation; associating a symbol to represent the condition in which a selected group of said status signals are asserted, said group including one or more of said status signals; operating said operative model of said logic circuit a predetermined number of periods of said clock signal; and outputting said symbol whenever said condition occurs at the end of each of said periods of said clock signal.
Claim 2
Independent Claim 135 words
A method for analyzing the performance of a logic circuit driven by a clock signal, comprising the steps of: identifying a number of operations of interest in said logic circuit, said logic circuit being an execution unit of a microprocessor; for each of said operations, creating in an operative model of said logic circuit a status signal, said status signal, when asserted, being representative of a status of said operation; associating a symbol to represent the condition in which a selected group of said status signals are asserted, said group including one or more of said status signals; operating said operative model of said logic circuit a predetermined number of periods of said clock signal; and outputting said symbol whenever said condition occurs at the end of each of said periods of said clock signal.
Claim 3
Dependent Claim 21 words
A method as in claim 1, wherein said operative model is a register transfer level (RTL) model of said logic circuit.
Claim 4
Dependent Claim 18 words
A method as in claim 1, wherein said execution unit executes multiple instructions of said microprocessor in parallel.
Claim 5
Dependent Claim 27 words
A method as in claim 3, wherein said operations of interest include the commitment of a result in the execution of said multiple instructions of said microprocessor.
Claim 6
Dependent Claim 20 words
A method as in claim 1, wherein said step of outputting said symbol outputs said symbol on a printed report.

References Cited (Backward Citations)

US4763289A Cited
US5179672A Cited
US5537580A Cited
US5666288A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-03-22 2002-09-21 2003-03-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-03-22 2006-09-21 2007-03-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-03-22 2010-09-21 2011-03-23 $7700.00 Window Closed / Lapsed

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