Abstract A method for analyzing the performance of a logic circuit driven by a clock signal, such as a microprocessor, identifies a number of operations of interest in a logic circuit and represents the presence of each of such operations by a different symbol. One or more of these symbols are output for perusal at the end of each clock period of operation. In one embodiment, this method is applied to a register transfer level (RTL) simulation of an execution unit of a microprocessor. In that embodiment, the execution sequence of multiple instructions executing simultaneously in the execution unit was analyzed. Because each output symbol represents a summary of a large number of activities that occur in a single clock period of operation or simulation of a complex logic circuit, these symbols can be tabulated in a format that allows a designer of the complex logic circuit to easily spot an unexpected pattern of operation, or an error condition.
A method for analyzing the performance of a logic circuit driven by a clock signal, comprising the steps of: identifying a number of operations of interest in said logic circuit, said logic circuit being an execution unit of a microprocessor; for each of said operations, creating in an operative model of said logic circuit a status signal, said status signal, when asserted, being representative of a status of said operation; associating a symbol to represent the condition in which a selected group of said status signals are asserted, said group including one or more of said status signals; operating said operative model of said logic circuit a predetermined number of periods of said clock signal; and outputting said symbol whenever said condition occurs at the end of each of said periods of said clock signal.
Claim 2
Independent Claim
135 words
A method for analyzing the performance of a logic circuit driven by a clock signal, comprising the steps of: identifying a number of operations of interest in said logic circuit, said logic circuit being an execution unit of a microprocessor; for each of said operations, creating in an operative model of said logic circuit a status signal, said status signal, when asserted, being representative of a status of said operation; associating a symbol to represent the condition in which a selected group of said status signals are asserted, said group including one or more of said status signals; operating said operative model of said logic circuit a predetermined number of periods of said clock signal; and outputting said symbol whenever said condition occurs at the end of each of said periods of said clock signal.
Claim 3
Dependent Claim
21 words
A method as in claim 1, wherein said operative model is a register transfer level (RTL) model of said logic circuit.
Claim 4
Dependent Claim
18 words
A method as in claim 1, wherein said execution unit executes multiple instructions of said microprocessor in parallel.
Claim 5
Dependent Claim
27 words
A method as in claim 3, wherein said operations of interest include the commitment of a result in the execution of said multiple instructions of said microprocessor.
Claim 6
Dependent Claim
20 words
A method as in claim 1, wherein said step of outputting said symbol outputs said symbol on a printed report.