Machine and method for simulating a processor-based digital system

Claim 2

A machine for testing a hypothetical system containing a processor and a digital device, the machine comprising: a simulation environment having a processor simulator and a digital environment, said digital environment emulating one or more pieces of digital hardware, said processor simulator and said digital environment processing independently of each other; and a significant event identifier to identify to the processor simulator one or more events that are significant to the digital environment, wherein said one or more events contain associated event information; interface means for conveying, to the digital environment, said event information from an instruction-oriented format to a bus signal format, wherein the digital environment receives and processes said event information, generating an event result, said interface means conveying said event result to the processor simulator.

Claim 3

The machine of claim 1, wherein said event information includes a time stamp indicating an amount of simulated time since the digital environment last received previous event information, and wherein, upon receiving said time stamp, the digital environment executes an appropriate number of bus cycles.

Claim 4

The machine of claim 2, wherein said time stamp is forwarded to the digital environment when no event information has been conveyed to the digital environment within a predetermined amount of time.

Claim 5

The machine of claim 2, wherein an interrupt generated by the digital environment is conveyed to the process simulator, and is processed upon receipt of said event result by the process simulator.

Claim 6

The machine of claim 1, wherein said event information includes a poll command for allowing a state of a specified simulated signal of the digital environment to be obtained and conveyed, by said interface means, to the processor simulator.

Claim 7

A machine for testing a hypothetical system containing a processor and a digital device, the machine comprising: a simulation environment having a processor simulator and a digital environment, said digital environment emulating one or more pieces of digital hardware, said processor simulator and said digital environment processing independently of each other; and a significant event identifier to identify to the processor simulator one or more events that are significant to the digital environment, wherein said one or more events contain associated event information; a digital simulator interface for conveying, to the digital environment, said event information, wherein the digital environment receives and processes said event information, generating an event result; and a processor simulator interface for conveying said event result to the processor simulator, wherein said digital simulator and said processor simulator translate said event information from an instruction-oriented format to a bus signal format, and vice versa.

Claim 8

A machine for testing a hypothetical system containing a processor and a digital device, the machine comprising: a simulation environment having a processor simulator and a digital environment, said digital environment emulating one or more pieces of digital hardware, said processor simulator and said digital environment processing independently of each other; and a significant event identifier to identify to the processor simulator one or more events that are significant to the digital environment, wherein said one or more events contain associated event information; a digital simulator interface for conveying, to the digital environment, said event information, wherein the digital environment receives and processes said event information, generating an event result; and a processor simulator interface for conveying said event result to the processor simulator, wherein said digital simulator and said processor simulator translate said event information from an instruction-oriented format to a bus signal format, and vice versa.

Claim 9

The machine of claim 6, wherein said one or more significant events comprise memory reads or memory writes.

Claim 10

The machine of claim 6, wherein said event information includes a time stamp indicating an amount of simulated time since the digital environment last received previous event information, and wherein, upon receiving said time stamp, the digital environment executes an appropriate number of bus cycles.

Claim 11

The machine of claim 8, wherein said time stamp is forwarded to the digital environment when no event information has been conveyed to the digital environment within a predetermined amount of time.

Claim 12

The machine of claim 8, wherein an interrupt generated by the digital environment is conveyed to the process simulator, and is processed upon receipt of said event result by the process simulator.

Claim 13

A machine for testing a hypothetical system containing a processor and a digital device, the machine comprising: a simulation environment having a processor simulator and a digital environment, said digital environment emulating one or more pieces of digital hardware, said processor simulator and said digital environment processing independently of each other; and a significant event identifier to identify to the processor simulator one or more events that are significant to the digital environment, wherein said one or more events contain associated event information; processor interface means for conveying, to the digital environment, said event information; digital interface means, for receiving said event information from said processor interface means, wherein said event information is translated from an instruction-oriented format to a bus signal format; digital resumption means, responsive to said digital interface means, for initiating or resuming activity on the digital environment, wherein the digital environment receives and processes said event information from said digital interface means, generating an event result, said interface means conveying said event result to the processor simulator through said digital interface means; and digital suspension means, responsive to said digital interface means, for suspending activity on the digital environment.

Claim 14

A machine for testing a hypothetical system containing a processor and a digital device, the machine comprising: a simulation environment having a processor simulator and a digital environment, said digital environment emulating one or more pieces of digital hardware, said processor simulator and said digital environment processing independently of each other; and a significant event identifier to identify to the processor simulator one or more events that are significant to the digital environment, wherein said one or more events contain associated event information; processor interface means for conveying, to the digital environment, said event information; digital interface means, for receiving said event information from said processor interface means, wherein said event information is translated from an instruction-oriented format to a bus signal format; digital resumption means, responsive to said digital interface means, for initiating or resuming activity on the digital environment, wherein the digital environment receives and processes said event information from said digital interface means, generating an event result, said interface means conveying said event result to the processor simulator through said digital interface means; and digital suspension means, responsive to said digital interface means, for suspending activity on the digital environment.

Claim 15

The machine of claim 11, further comprising processor suspension means, responsive to said processor interface means, for suspending activity on the processor simulator, and processor resumption means, responsive to said processor interface means, for resuming activity on the processor simulator.

Claim 16

The machine of claim 12, wherein said processor suspension and resumption means, and said digital suspension and resumption means utilize UNIX named pipes.

Claim 17

The machine of claim 11, wherein said event information includes a time stamp indicating an amount of simulated time since the digital environment last received previous event information, and wherein, upon receiving said time stamp, the digital environment executes an appropriate number of bus cycles.

Claim 18

The machine of claim 14, wherein said time stamp is forwarded to the digital environment when no event information has been conveyed to the digital environment within a predetermined amount of time.

Claim 19

The machine of claim 14, wherein an interrupt generated by the digital environment is conveyed to the process simulator, and is processed upon receipt of said event result by the process simulator.

Claim 20

A procedure for testing a hypothetical system containing a processor and a digital device, wherein the process utilizes a simulation environment having a processor simulator and a digital environment running as independent processes, comprising the steps of: (1) identifying one or more events that are significant to the digital environment, wherein said one or more events contains associated event information; (2) conveying, to the digital environment, said event information of said step (1); (3) translating said event information conveyed by said step (2) from an instruction-oriented format to a bus signal format, wherein the digital environment receives and processes said event information, generating an event result; (4) conveying said event result of said step (3) to the processor simulator.

Claim 21

A procedure for testing a hypothetical system containing a processor and a digital device, wherein the process utilizes a simulation environment having a processor simulator and a digital environment running as independent processes, comprising the steps of: (1) identifying one or more events that are significant to the digital environment, wherein said one or more events contains associated event information; (2) conveying, to the digital environment, said event information of said step (1); (3) translating said event information conveyed by said step (2) from an instruction-oriented format to a bus signal format, wherein the digital environment receives and processes said event information, generating an event result; (4) conveying said event result of said step (3) to the processor simulator.

Claim 22

The procedure of claim 17, wherein said event information of said step (1) includes a time stamp indicating an amount of simulated time since the digital environment last received previous event information, and wherein, upon receiving said time stamp, the digital environment executes an appropriate number of bus cycles.

Claim 23

The procedure of claim 18, wherein said time stamp is forwarded to the digital environment when no event information has been conveyed to the digital environment within a predetermined amount of time.

Claim 24

The procedure of claim 17, wherein said event information of said step (1) includes a poll command for allowing a state of a specified simulated signal of the digital environment to be obtained and conveyed to the processor simulator.