Patent US6566208B2 successfully refreshed from Google Patents.
US6566208B2
Expired / Lapsed
US
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Method to form elevated source/drain using poly spacer
Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 2001-07-25
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Granted: 2003-05-20
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Expires: 2021-07-25
Abstract
Abstract A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers. The polysilicon spacer on an end of the gate electrode is removed to separate the polysilicon spacers into a source polysilicon spacer and a drain polysilicon spacer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.
Inventors
- 👤 Yang Pan
- 👤 Lee Yong Meng
- 👤 Leung Ying Keung
- 👤 Yelehanka Ramachandramurthy Pradeep
- 👤 Jia Zhen Zheng
- 👤 Lap Chan
- 👤 Elgin Quek
- 👤 Ravi Sundarensan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:43
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0212; H10D64/00; H10D64/01; H10D64/021; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
203 words
A method of forming a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device comprising: forming a gate electrode over a gate dielectric on a substrate; implanting ions into said substrate to form lightly doped regions using said gate electrode as a mask; thereafter forming dielectric spacers on sidewalls of said gate electrode; depositing a polysilicon layer overlying said substrate, said gate electrode, and said dielectric spacers wherein said polysilicon layer is heavily doped; anisotropically etching back said polysilicon layer to leave polysilicon spacers on said dielectric spacers; diffusing dopant from said polysilicon spacers into said substrate to form source and drain extension regions underlying said polysilicon spacers; removing said polysilicon spacer on an end of said gate electrode to separate said polysilicon spacers into a source polysilicon spacer and a drain polysilicon spacer thereby completing formation of said elevated source/drain structure; thereafter depositing an insulating layer overlying said elevated source/drain structure and forming contact openings in said insulating layer to expose said lightly doped regions, said source polysilicon spacer, and said drain polysilicon spacer; and depositing a contact layer within said contact openings to form an electrical connection to complete fabrication of said MOSFET integrated circuit device.
Claim 2
Independent Claim
203 words
A method of forming a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device comprising: forming a gate electrode over a gate dielectric on a substrate; implanting ions into said substrate to form lightly doped regions using said gate electrode as a mask; thereafter forming dielectric spacers on sidewalls of said gate electrode; depositing a polysilicon layer overlying said substrate, said gate electrode, and said dielectric spacers wherein said polysilicon layer is heavily doped; anisotropically etching back said polysilicon layer to leave polysilicon spacers on said dielectric spacers; diffusing dopant from said polysilicon spacers into said substrate to form source and drain extension regions underlying said polysilicon spacers; removing said polysilicon spacer on an end of said gate electrode to separate said polysilicon spacers into a source polysilicon spacer and a drain polysilicon spacer thereby completing formation of said elevated source/drain structure; thereafter depositing an insulating layer overlying said elevated source/drain structure and forming contact openings in said insulating layer to expose said lightly doped regions, said source polysilicon spacer, and said drain polysilicon spacer; and depositing a contact layer within said contact openings to form an electrical connection to complete fabrication of said MOSFET integrated circuit device.
Claim 3
Dependent Claim
45 words
The method according to claim 1 wherein said step of forming said dielectric spacers comprises: depositing an oxide layer overlying said semiconductor substrate and said gate electrode; and etching back said oxide layer to leave said dielectric spacers only on sidewalls of said gate electrode.
Claim 4
Dependent Claim
66 words
The method according to claim 1 wherein said step of forming said dielectric spacers comprises: oxidizing said semiconductor substrate and said gate electrode to form an oxide layer overlying said semiconductor substrate and said gate electrode; and etching away said oxide layer overlying said semiconductor substrate and a top surface of said gate electrode to leave said dielectric spacers only on sidewalls of said gate electrode.
Claim 5
Dependent Claim
24 words
The method according to claim 1 wherein said polysilicon layer is deposited by LPCVD to a thickness of between about 500 and 4000 Angstroms.
Claim 6
Dependent Claim
13 words
The method according to claim 1 wherein said polysilicon layer is in-situ doped.
Claim 7
Dependent Claim
15 words
The method according to claim 1 wherein said polysilicon layer is doped by ion implantation.
Claim 8
Dependent Claim
25 words
The method according to claim 1 wherein said polysilicon layer has a dopant concentration of between about 10 20 and 10 22 atoms/cm 3 .
Claim 9
Independent Claim
221 words
A method of forming a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device comprising: forming a gate electrode over a gate dielectric on a substrate; implanting ions into said substrate to form lightly doped regions using said gate electrode as a mask; thereafter forming dielectric spacers on sidewalls of said gate electrode; depositing a polysilicon layer overlying said substrate, said gate electrode, and said dielectric spacers wherein said polysilicon layer is heavily doped; anisotropically etching back said polysilicon layer to leave polysilicon spacers on said dielectric spacers wherein said polysilicon spacers form elevated source/drain regions; diffusing dopant from said elevated source/drain regions into said substrate using a rapid thermal process to form source and drain extension regions underlying said elevated source/drain regions; and removing said polysilicon spacer on an end of said gate electrode to separate said elevated source/drain regions into an elevated source region and an elevated drain region thereby completing formation of said elevated source/drain structure; thereafter depositing an insulating layer overlying said elevated source/drain structure and forming contact openings in said insulating layer to expose said lightly doped regions, said source polysilicon spacer, and said drain polysilicon spacer; and depositing a contact layer within said contact openings to form an electrical connection to complete fabrication of said MOSFET integrated circuit 35 device.
Claim 10
Independent Claim
221 words
A method of forming a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device comprising: forming a gate electrode over a gate dielectric on a substrate; implanting ions into said substrate to form lightly doped regions using said gate electrode as a mask; thereafter forming dielectric spacers on sidewalls of said gate electrode; depositing a polysilicon layer overlying said substrate, said gate electrode, and said dielectric spacers wherein said polysilicon layer is heavily doped; anisotropically etching back said polysilicon layer to leave polysilicon spacers on said dielectric spacers wherein said polysilicon spacers form elevated source/drain regions; diffusing dopant from said elevated source/drain regions into said substrate using a rapid thermal process to form source and drain extension regions underlying said elevated source/drain regions; and removing said polysilicon spacer on an end of said gate electrode to separate said elevated source/drain regions into an elevated source region and an elevated drain region thereby completing formation of said elevated source/drain structure; thereafter depositing an insulating layer overlying said elevated source/drain structure and forming contact openings in said insulating layer to expose said lightly doped regions, said source polysilicon spacer, and said drain polysilicon spacer; and depositing a contact layer within said contact openings to form an electrical connection to complete fabrication of said MOSFET integrated circuit 35 device.
Claim 11
Dependent Claim
45 words
The method according to claim 8 wherein said step of forming said dielectric spacers comprises: depositing an oxide layer overlying said semiconductor substrate and said gate electrode; and etching back said oxide layer to leave said dielectric spacers only on sidewalls of said gate electrode.
Claim 12
Dependent Claim
66 words
The method according to claim 8 wherein said step of forming said dielectric spacers comprises: oxidizing said semiconductor substrate and said gate electrode to form an oxide layer overlying said semiconductor substrate and said gate electrode; and etching away said oxide layer overlying said semiconductor substrate and a top surface of said gate electrode to leave said dielectric spacers only on sidewalls of said gate electrode.
Claim 13
Dependent Claim
13 words
The method according to claim 8 wherein said polysilicon layer is in-situ doped.
Claim 14
Dependent Claim
15 words
The method according to claim 8 wherein said polysilicon layer is doped by ion implantation.
Claim 15
Dependent Claim
25 words
The method according to claim 8 wherein said polysilicon layer has a dopant concentration of between about 10 20 and 10 22 atoms/cm 3 .
Claim 16
Dependent Claim
24 words
The method according to claim 8 wherein said polysilicon layer is deposited by LPCVD to a thickness of between about 500 and 4000 Angstroms.
Claim 17
Independent Claim
234 words
A method of forming a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device comprising: forming a gate electrode over a gate dielectric on a substrate; implanting ions into said substrate to form lightly doped regions using said gate electrode as a mask; thereafter depositing a dielectric layer overlying said semiconductor substrate and said gate electrode; etching back said dielectric layer to leave dielectric spacers only on sidewalls of said gate electrode; depositing a polysilicon layer overlying said substrate, said gate electrode, and said dielectric spacers wherein said polysilicon layer is heavily doped; anisotropically etching back said polysilicon layer to leave polysilicon spacers on said dielectric spacers wherein said polysilicon spacers form elevated source/drain regions; diffusing dopant from said elevated source/drain regions into said substrate to form source and drain extension regions underlying said elevated source/drain regions; and removing said polysilicon spacer on an end of said gate electrode to separate said elevated source/drain regions into an elevated source region and an elevated drain region thereby completing formation of said elevated source/drain structure; thereafter depositing an insulating layer overlying said elevated source/drain structure and forming contact openings in said insulating layer to expose said lightly doped regions, said source polysilicon spacer, and said drain polysilicon spacer; and depositing a contact layer within said contact openings to form an electrical connection to complete fabrication of said MOSFET integrated circuit device.
Claim 18
Independent Claim
234 words
A method of forming a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device comprising: forming a gate electrode over a gate dielectric on a substrate; implanting ions into said substrate to form lightly doped regions using said gate electrode as a mask; thereafter depositing a dielectric layer overlying said semiconductor substrate and said gate electrode; etching back said dielectric layer to leave dielectric spacers only on sidewalls of said gate electrode; depositing a polysilicon layer overlying said substrate, said gate electrode, and said dielectric spacers wherein said polysilicon layer is heavily doped; anisotropically etching back said polysilicon layer to leave polysilicon spacers on said dielectric spacers wherein said polysilicon spacers form elevated source/drain regions; diffusing dopant from said elevated source/drain regions into said substrate to form source and drain extension regions underlying said elevated source/drain regions; and removing said polysilicon spacer on an end of said gate electrode to separate said elevated source/drain regions into an elevated source region and an elevated drain region thereby completing formation of said elevated source/drain structure; thereafter depositing an insulating layer overlying said elevated source/drain structure and forming contact openings in said insulating layer to expose said lightly doped regions, said source polysilicon spacer, and said drain polysilicon spacer; and depositing a contact layer within said contact openings to form an electrical connection to complete fabrication of said MOSFET integrated circuit device.
Claim 19
Dependent Claim
13 words
The method according to claim 15 wherein said polysilicon layer is in-situ doped.
Claim 20
Dependent Claim
15 words
The method according to claim 15 wherein said polysilicon layer is doped by ion implantation.
Claim 21
Dependent Claim
25 words
The method according to claim 15 wherein said polysilicon layer has a dopant concentration of between about 10 20 and 10 22 atoms/cm 3 .
Claim 22
Dependent Claim
33 words
The method according to claim 15 wherein said step of diffusing dopant from said polysilicon spacers into said semiconductor substrate to form source and drain regions is performed by a rapid thermal process.
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