Method of producing an interconnect structure for an integrated circuit

Claim 2

A digital storage medium containing a computer program that, when executed by a computer, causes the computer to operate a semiconductor wafer processing system to form an interconnect structure by performing the steps of: (a) depositing a first insulator layer upon a substrate; (b) depositing an etch stop layer upon said first insulator layer; (c) depositing a second insulator layer on top of said etch stop layer; (d) forming a first mask atop of said second insulator layer; (e) etching said first insulator layer, said etch stop layer and said second insulator layer in a single step to define a via; (f) removing said first mask; (g) forming a second mask to define a trench; (h) etching said second insulator layer as defined by said second mask to form a trench; and (i) metalizing said via and said trench to form an interconnect structure.

Claim 3

The digital storage medium of claim 1 wherein said program stored therein, when executed, further causes the semiconductor wafer processing system to form the first mask by the following steps: applying a photoresist material onto said second insulator layer; developing said photoresist; and patterning said photoresist to define a location and dimension of said via.

Claim 4

The digital storage medium of claim 2 wherein the photoresist is not developed completely within said via.

Claim 5

The digital storage medium of claim 1 wherein said program stored therein, when executed, further causes the semiconductor wafer processing system to form the second mask is formed by the following steps: applying a photoresist material onto said second insulator layer; developing said photoresist; and patterning said photoresist to define a location and dimension of said trench.

Claim 6

The digital storage medium of claim 1 wherein said program stored therein, when executed, further causes the semiconductor wafer processing system to perform the steps of forming a second level of interconnect structure containing a second via and a second trench by passivating said metallization and then repeating steps (a) through (h), then etching a passivation layer to expose said metallization at a bottom of said second via and metalizing said second via and trench.

Claim 7

The digital storage medium of claim 1 wherein said etching step which forms said via is a reactive ion etch.

Claim 8

The digital storage medium of claim 1 wherein said etch of said trench in the second insulator layer is a reactive ion etch.

Claim 9

The digital storage medium of claim 1 wherein said first insulator layer and said second insulator layer are made of silicon dioxide.

Claim 10

The digital storage medium of claim 1 wherein said first insulator layer or said second insulator layer or both are made of a low dielectric constant material.

Claim 11

The digital storage medium of claim 1 wherein the etching performed in step (e) is conducted using one etch chemistry.

Claim 12

A digital storage medium containing a computer program that, when executed by a computer, causes the computer to operate a semiconductor wafer processing system to form an interconnect structure by performing the steps of: (a) depositing a first insulator layer upon a substrate; (b) depositing an etch stop layer upon said first insulator layer; (c) depositing a second insulator layer on top of said etch stop layer; (d) forming a first mask atop of said second insulator layer; (e) etching said first insulator layer, said etch stop layer and said second insulator layer in a single step to define a via; (f) removing said first mask; (g) forming a second mask to define a trench; (h) etching said second insulator layer as defined by said second mask to form a trench; (i) metalizing said via and said trench to form an interconnect structure; (j) planarizing said metallization; (k) forming a passivation layer over said planarized metallization; (l) repeating steps (a)-(h) to form a second level of interconnect structure contains a second via and second trench; (m) removing said passivation layer at a bottom of said second via; and (n) metalizing said second via and said second trench to form a second layer for said interconnect structure.

Claim 13

A digital storage medium containing a computer program that, when executed by a computer, causes the computer to operate a semiconductor wafer processing system to form an interconnect structure by performing the steps of: (a) depositing a first insulator layer upon a substrate; (b) depositing an etch stop layer upon said first insulator layer; (c) depositing a second insulator layer on top of said etch stop layer; (d) forming a first mask atop of said second insulator layer; (e) etching said first insulator layer, said etch stop layer and said second insulator layer in a single step to define a via; (f) removing said first mask; (g) forming a second mask to define a trench; (h) etching said second insulator layer as defined by said second mask to form a trench; (i) metalizing said via and said trench to form an interconnect structure; (j) planarizing said metallization; (k) forming a passivation layer over said planarized metallization; (l) repeating steps (a)-(h) to form a second level of interconnect structure contains a second via and second trench; (m) removing said passivation layer at a bottom of said second via; and (n) metalizing said second via and said second trench to form a second layer for said interconnect structure.

Claim 14

The digital storage medium of claim 11 wherein said first mask is formed by the following steps: applying a photoresist material onto said second insulator layer; developing said photoresist; and patterning said photoresist to define a location and dimension of said via.

Claim 15

The digital storage medium of claim 11 wherein said second mask is formed by the following steps: applying a photoresist material onto said second insulator layer; developing said photoresist; and patterning said photoresist to define a location and dimension of said trench.

Claim 16

The digital storage medium of claim 13 wherein the photoresist is not developed completely within said via.

Claim 17

The digital storage medium of claim 11 wherein said etching step which forms said via is a combination of a reactive ion etch and an isotropic etch.

Claim 18

The digital storage medium of claim 11 wherein said etch of said trench in the second insulator layer is a reactive ion etch.

Claim 19

The digital storage medium of claim 11 wherein said first insulator layer and said second insulator layer are made of silicon dioxide.

Claim 20

The digital storage medium of claim 11 wherein said first insulator layer or said second insulator layer or both are made of a low dielectric constant material.

Claim 21

The digital storage medium of claim 11 wherein the etching performed in step (e) is conducted using one etch chemistry.