Three-dimensional (3D) programmable device

Claim 2

A memory device comprising: a plurality of memory cells each memory cell comprising a programmable portion and an isolation element, the isolation element displaced in an opening formed through an insulation material separating the programmable portion from a signal line, the programmable portion coupled to the signal line through the isolation element and an electrode, wherein a first programmable portion of a first memory cell is formed in a first plane over a substrate and a second programmable portion of a second memory cell is formed in a second different plane to form a three-dimensional (3D) memory array, wherein the electrode is formed on the isolation element and along a wall of an opening through the insulation material.

Claim 3

The memory device of claim 1 , where each isolation element is a polysilicon diode.

Claim 4

The memory device of claim 1 , wherein the programmable portion of each memory cell is a chalcogenide material.

Claim 5

The memory device of claim 1 , further comprising: a base insulator layer to support the plurality of stacked memory cells.

Claim 6

The memory device of claim 1 further comprising: an insulating layer between the first plane and the second plane.

Claim 7

The memory device according to claim 1 , further comprising: a second insulation material formed on the electrode.

Claim 8

A memory device comprising: a plurality of memory cells each memory cell comprising a chalcogenide portion, wherein a first chalcogenide portion of a first memory cell is formed in a first plane over a substrate and a second chalcogenide portion of a second memory cell is formed in a second different plane in a three dimensional (3D) array; a plurality of isolation elements, each isolation element used to select one of the plurality of chalcogenide memory cells; and a plurality of signal lines, ones of the plurality of signal lines coupled to at least one of the plurality of memory cells, respective ones of the plurality of isolation elements and an electrode separating the ones of the plurality of signal lines and the at least one of the plurality of memory cells, wherein the respective ones of the plurality of isolation elements are displaced in openings formed through insulation material separating the at least one memory cell and the ones of the plurality of signal lines, wherein the electrode is formed on the isolation element and along a wall of an opening through the insulation material.

Claim 9

A memory device comprising: a plurality of memory cells each memory cell comprising a chalcogenide portion, wherein a first chalcogenide portion of a first memory cell is formed in a first plane over a substrate and a second chalcogenide portion of a second memory cell is formed in a second different plane in a three dimensional (3D) array; a plurality of isolation elements, each isolation element used to select one of the plurality of chalcogenide memory cells; and a plurality of signal lines, ones of the plurality of signal lines coupled to at least one of the plurality of memory cells, respective ones of the plurality of isolation elements and an electrode separating the ones of the plurality of signal lines and the at least one of the plurality of memory cells, wherein the respective ones of the plurality of isolation elements are displaced in openings formed through insulation material separating the at least one memory cell and the ones of the plurality of signal lines, wherein the electrode is formed on the isolation element and along a wall of an opening through the insulation material.

Claim 10

The memory device of claim 7 , wherein each isolation element is a polysilicon diode isolation element.

Claim 11

The memory device of claim 7 , wherein the ones of the plurality of signal lines are first address lines, the memory device further comprising: a plurality of second address lines, one of the plurality of second address lines coupled to the at least one of the plurality coupled to the memory cells.

Claim 12

The memory device of claim 7 , further comprising: a base insulation layer to support the plurality of memory cells and isolation elements.

Claim 13

The memory device of claim 7 further comprising: an insulating layer between the first plane and the second plane.

Claim 14

The memory device according to claim 7 , further comprising: a second insulation material formed on the electrode.

Claim 15

A memory device comprising: a plurality of memory cells each memory cell comprising a chalcogenide portion, wherein a first chalcogenide portion of a first memory cell is formed in a first plane over a substrate and a second chalcogenide portion of a second memory cell is formed in a second different plane in a three dimensional (3D) array; a plurality of isolation elements, each isolation element used to select one at the plurality of chalcogenide memory cells; and a plurality of signal lines, ones of the plurality of signal lines coupled to at least one of the plurality of memory cells, respective ones of the plurality of isolation elements and an electrode separating the ones of the plurality of signal lines and the at least one of the plurality of memory cells, wherein the electrode has a vertical portion and a horizontal portion, the vertical portion coupled to a portion of the lower surface of the first chalcogenide portions.

Claim 16

A memory device comprising: a plurality of memory cells each memory cell comprising a chalcogenide portion, wherein a first chalcogenide portion of a first memory cell is formed in a first plane over a substrate and a second chalcogenide portion of a second memory cell is formed in a second different plane in a three dimensional (3D) array; a plurality of isolation elements, each isolation element used to select one at the plurality of chalcogenide memory cells; and a plurality of signal lines, ones of the plurality of signal lines coupled to at least one of the plurality of memory cells, respective ones of the plurality of isolation elements and an electrode separating the ones of the plurality of signal lines and the at least one of the plurality of memory cells, wherein the electrode has a vertical portion and a horizontal portion, the vertical portion coupled to a portion of the lower surface of the first chalcogenide portions.