Patent US6499123B1 successfully refreshed from Google Patents.
US6499123B1
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US
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Method and apparatus for debugging an integrated circuit
Assignee: Advanced Micro Devices Inc
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Filing: 2000-04-12
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Granted: 2002-12-24
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Expires: 2020-04-12
Abstract
Abstract An integrated circuit having a normal mode for operating under normal operating conditions and a debug mode for operating to test and debug the integrated circuit. The integrated circuit includes a plurality of output pins that carry a first plurality of signals in the normal mode and carry a second plurality of signals in the debug mode. In one embodiment, the integrated circuit embodies a microprocessor. The microprocessor may include logic circuitry for enabling the second plurality of signals to be output from a multiplexer to the output pins in response to a predetermined event, such as a hit in an associated memory unit.
Inventors
- 👤 Harold L. McFarland
- 👤 David R. Stiles
- 👤 Korbin S. Van Dyke
- 👤 Shrenik Mehta
- 👤 John Gregory Favor
- 👤 Dale R. Greenley
- 👤 Robert A. Cargnoni
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:40
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/364; G06F11/3648; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/14; G06F12/1416; G06F12/145; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F9/30003; G06F9/30007; G06F9/30018; G06F9/30036; G06F9/30038; G06F9/3005; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/3017; G06F9/30174; G06F9/30181; G06F9/30185; G06F9/30189; G06F9/32; G06F9/322; G06F9/323; G06F9/355; G06F9/3555; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3812; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3842; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/38585; G06F9/3861; G06F9/3863; G06F9/3867; G06F9/3869; G06F9/3885
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
157 words
A microprocessor having a normal mode for operation under normal operating conditions and a debug mode for operations to test and debug the microprocessor, comprising: a cache memory unit; a plurality of execution units; a plurality of output pins; a plurality of internal busses, wherein the plurality of execution units are interconnected through the plurality of internal busses; multiplexer circuitry having a first input coupled to the plurality of internal busses and a second input coupled the cache memory unit; and test control logic for setting the multiplexer in either the normal mode or the debug mode; wherein during the normal mode, external data requests resulting from misses in the cache memory unit are conveyed through the second input of the multiplexer circuitry to the output pins; and wherein during the debug mode, at least some signals of the plurality of internal busses are conveyed through the first input of the multiplexer circuitry to the output pins.
Claim 2
Dependent Claim
157 words
A microprocessor having a normal mode for operation under normal operating conditions and a debug mode for operations to test and debug the microprocessor, comprising: a cache memory unit; a plurality of execution units; a plurality of output pins; a plurality of internal busses, wherein the plurality of execution units are interconnected through the plurality of internal busses; multiplexer circuitry having a first input coupled to the plurality of internal busses and a second input coupled the cache memory unit; and test control logic for setting the multiplexer in either the normal mode or the debug mode; wherein during the normal mode, external data requests resulting from misses in the cache memory unit are conveyed through the second input of the multiplexer circuitry to the output pins; and wherein during the debug mode, at least some signals of the plurality of internal busses are conveyed through the first input of the multiplexer circuitry to the output pins.
Claim 3
Dependent Claim
34 words
The microprocessor of claim 1 wherein the test control logic includes a test register for storing a value that controls which signals of the plurality of internal busses are conveyed to the output pins.
Claim 4
Dependent Claim
40 words
The microprocessor of claim 2 , wherein the multiplexer circuitry is configured to cause the signals of the internal busses to be conveyed to the ouput pins during said debug mode in response to an occurrence of a predetermined event.
Claim 5
Dependent Claim
21 words
The microprocessor of claim 3 wherein the predetermined event is an occurrence of a cache hit in said cache memory unit.
Claim 6
Dependent Claim
23 words
The integrated circuit of claim 1 wherein the internal signals are not visible on the output pins while operating in the normal mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-12-23 | 2006-06-24 | 2006-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-23 | 2010-06-24 | 2010-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-23 | 2014-06-24 | 2014-12-24 | $7700.00 | Window Closed / Lapsed |