US6455372B1
Expired / Lapsed
US
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Nucleation for improved flash erase characteristics
Assignee: Micron Technology Inc
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Filing: 2000-08-14
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Granted: 2002-09-24
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Expires: 2020-08-14
Abstract
Abstract The present invention provides a method for improving the erase speed and the uniformity of erase characteristics in erasable programmable read-only memories. This result is achieved by forming polycrystalline floating gate layers with optimized grain size on a tunnel dielectric layer. Nucleation sites are formed by exposing the tunnel dielectric layer to a first set of conditions including a first temperature and a first atmosphere selected to optimize nucleation site size and distribution density across the tunnel dielectric layer. A polycrystalline floating gate layer is formed on top of the nucleation sites by exposing the nucleation sites to a second set of conditions including a second temperature and a second atmosphere selected to optimize polycrystalline grain size and distribution density across the polycrystalline floating gate layer.
Inventors
- 👤 Ronald A. Weimer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:47
CPC Classifications
B; B82; B82Y; B82Y10/00; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/661; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/36; H10P14/3602; H10P14/40
Claims Analysis
Total Claims: 56
Claim 1
Independent Claim
91 words
A method of tailoring the crystal morphology of a polysilicon floating gate layer in a flash memory device, the method comprising: forming a tunnel dielectric layer; depositing nucleation sites on top of the tunnel dielectric layer under a first set of deposition conditions comprising a first temperature and a first atmosphere; and depositing a polysilicon layer on top of the nucleation sites under a second set of deposition conditions different from the first set of deposition conditions, the second set of deposition conditions comprising a second temperature and a second atmosphere.
Claim 2
Independent Claim
91 words
A method of tailoring the crystal morphology of a polysilicon floating gate layer in a flash memory device, the method comprising: forming a tunnel dielectric layer; depositing nucleation sites on top of the tunnel dielectric layer under a first set of deposition conditions comprising a first temperature and a first atmosphere; and depositing a polysilicon layer on top of the nucleation sites under a second set of deposition conditions different from the first set of deposition conditions, the second set of deposition conditions comprising a second temperature and a second atmosphere.
Claim 3
Dependent Claim
18 words
The method of claim 1 , wherein the first temperature is between approximately 500° C. and 650° C.
Claim 4
Dependent Claim
18 words
The method of claim 2 , wherein the first temperature is between approximately 575° C. and 630° C.
Claim 5
Dependent Claim
21 words
The method of claim 1 , wherein the first temperature is selected to optimize a grain structure of the nucleation sites.
Claim 6
Dependent Claim
23 words
The method of claim 4 , wherein the second temperature is selected to optimize a grain size of the polysilicon floating gate layer.
Claim 7
Dependent Claim
18 words
The method of claim 1 , wherein the second temperature is between approximately 450° C. and 700° C.
Claim 8
Dependent Claim
18 words
The method of claim 6 , wherein the second temperature is between approximately 500° C. and 700° C.
Claim 9
Dependent Claim
18 words
The method of claim 7 , wherein the second temperature is between approximately 530° C. and 650° C.
Claim 10
Dependent Claim
26 words
The method of claim 1 , wherein the nucleation sites are formed in a vacuum chamber and the polysilicon layer is deposited in the vacuum chamber.
Claim 11
Dependent Claim
16 words
The method of claim 1 , wherein the nucleation sites are deposited in a single-wafer chamber.
Claim 12
Dependent Claim
15 words
The method of claim 10 , wherein the first atmosphere comprises a first hydride species.
Claim 13
Dependent Claim
14 words
The method of claim 11 , wherein the first hydride species comprises a silane.
Claim 14
Dependent Claim
26 words
The method of claim 11 , wherein the first hydride species is selected from a group consisting of SiH 4 and Si 2 H 6 .
Claim 15
Dependent Claim
24 words
The method of claim 11 , wherein the first hydride species has a partial pressure between approximately 10 −7 Torr and 10 −2 Torr.
Claim 16
Dependent Claim
24 words
The method of claim 11 , wherein the first hydride species has a partial pressure between approximately 10 −5 Torr and 10 −3 Torr.
Claim 17
Dependent Claim
29 words
The method of claim 11 , wherein the first hydride species has a partial pressure selected to optimize a distribution density of nucleation sites across the tunnel dielectric layer.
Claim 18
Dependent Claim
23 words
The method of claim 11 , wherein the first hydride species has a gas flow rate between approximately 1 sccm and 100 sccm.
Claim 19
Dependent Claim
23 words
The method of claim 17 , wherein the first hydride species has a gas flow rate between approximately 10 sccm and 30 sccm.
Claim 20
Dependent Claim
29 words
The method of claim 11 , wherein the tunnel dielectric layer is exposed to the first set of conditions for a time between approximately 10 seconds and 3 minutes.
Claim 21
Dependent Claim
29 words
The method of claim 11 , wherein the tunnel dielectric layer is exposed to the first set of conditions for a time between approximately 30 seconds and 90 seconds.
Claim 22
Dependent Claim
15 words
The method of claim 11 , wherein the second atmosphere comprises a second hydride species.
Claim 23
Dependent Claim
25 words
The method of claim 21 , wherein the second hydride species is the same as a first hydride species used to deposit the nucleation sites.
Claim 24
Dependent Claim
22 words
The method of claim 21 , wherein the second hydride species has a partial pressure between approximately 0.1 Torr and 10 Torr.
Claim 25
Dependent Claim
29 words
The method of claim 10 , wherein the nucleation sites are exposed to the second set of deposition conditions for a time between approximately 1 second and 10 minutes.
Claim 26
Dependent Claim
29 words
The method of claim 10 , wherein the nucleation sites are exposed to the second set of deposition conditions for a time between approximately 1 minute and 5 minutes.
Claim 27
Dependent Claim
17 words
The method of claim 1 , wherein the polysilicon layer is deposited in a multi-wafer process chamber.
Claim 28
Dependent Claim
15 words
The method of claim 26 , wherein the first atmosphere comprises a first hydride species.
Claim 29
Dependent Claim
26 words
The method of claim 27 , wherein the first hydride species is selected from a group consisting of SiH 4 and Si 2 H 6 .
Claim 30
Dependent Claim
24 words
The method of claim 27 , wherein the first hydride species has a partial pressure between approximately 10 −7 Torr and 10 −2 Torr.
Claim 31
Dependent Claim
24 words
The method of claim 27 , wherein the first hydride species has a partial pressure between approximately 10 −7 Torr and 10 −3 Torr.
Claim 32
Dependent Claim
24 words
The method of claim 27 , wherein the first hydride species has a partial pressure between approximately 10 −5 Torr and 10 −3 Torr.
Claim 33
Dependent Claim
29 words
The method of claim 27 , wherein the first hydride species has a partial pressure selected to optimize a distribution density of nucleation sites across the tunnel dielectric layer.
Claim 34
Dependent Claim
23 words
The method of claim 27 , wherein the first hydride species has a partial pressure rate between approximately 1 mTorr and 100 mTorr.
Claim 35
Dependent Claim
23 words
The method of claim 27 , wherein the first hydride species has a partial pressure rate between approximately 10 mTorr and 50 mTorr.
Claim 36
Dependent Claim
19 words
The method of claim 27 , wherein the first atmosphere further comprises Ar, Ne, He, or N 2 .
Claim 37
Dependent Claim
30 words
The method of claim 27 , wherein the tunnel dielectric layer is exposed to the first set of deposition conditions for a time between approximately 5 minutes and 60 minutes.
Claim 38
Dependent Claim
30 words
The method of claim 36 , wherein the tunnel dielectric layer is exposed to the first set of deposition conditions for a time between approximately 10 minutes and 30 minutes.
Claim 39
Dependent Claim
15 words
The method of claim 27 , wherein the second atmosphere comprises a second hydride species.
Claim 40
Dependent Claim
25 words
The method of claim 38 , wherein the second hydride species is the same as a first hydride species used to deposit the nucleation sites.
Claim 41
Dependent Claim
22 words
The method of claim 38 , wherein the second hydride species has a partial pressure between approximately 0.1 Torr and 10 Torr.
Claim 42
Dependent Claim
15 words
The method of claim 38 , wherein the second atmosphere further comprises an inert gas.
Claim 43
Dependent Claim
29 words
The method of claim 26 , wherein the nucleation sites are exposed to the second set of deposition conditions for a time between approximately 1 minute and 60 minutes.
Claim 44
Dependent Claim
29 words
The method of claim 26 , wherein the nucleation sites are exposed to the second set of deposition conditions for a time between approximately 10 minutes and 45 minutes.
Claim 45
Independent Claim
91 words
A method of tailoring the erase speed and erase uniformity of a flash memory device, the method comprising: forming a tunnel dielectric layer; depositing nucleation sites on top of the tunnel dielectric layer by exposing the tunnel dielectric layer to a first set of deposition conditions; and depositing a polysilicon floating gate layer on top of the nucleation sites by exposing the nucleation sites to a second set of deposition conditions different from the first set of deposition conditions, the polysilicon floating gate layer having tailored polysilicon grain sizes and density.
Claim 46
Independent Claim
91 words
A method of tailoring the erase speed and erase uniformity of a flash memory device, the method comprising: forming a tunnel dielectric layer; depositing nucleation sites on top of the tunnel dielectric layer by exposing the tunnel dielectric layer to a first set of deposition conditions; and depositing a polysilicon floating gate layer on top of the nucleation sites by exposing the nucleation sites to a second set of deposition conditions different from the first set of deposition conditions, the polysilicon floating gate layer having tailored polysilicon grain sizes and density.
Claim 47
Dependent Claim
19 words
The method of claim 44 , wherein the polysilicon grain sizes are between approximately 25 Å and 500 Å.
Claim 48
Dependent Claim
19 words
The method of claim 45 , wherein the polysilicon grain sizes are between approximately 50 Å and 200 Å.
Claim 49
Dependent Claim
24 words
The method of claim 44 , wherein the polysilicon grain density is between approximately 5 per μm 2 and 100 per μm 2 .
Claim 50
Dependent Claim
24 words
The method of claim 47 , wherein the polysilicon grain density is between approximately 20 per μm 2 and 80 per μm 2 .
Claim 51
Dependent Claim
24 words
The method of claim 48 , wherein the polysilicon grain density is between about 30 per μm 2 and 60 per μm 2 .
Claim 52
Dependent Claim
18 words
The method of claim 44 , wherein the erase speed is between approximately 100 μ-sec and 100 m-sec.
Claim 53
Dependent Claim
18 words
The method of claim 44 , wherein the erase speed is between approximately 100 μ-sec and 1 m-sec.
Claim 54
Dependent Claim
18 words
The method of claim 44 , wherein the erase speed is between approximately 100 μ-sec and 150 m-sec.
Claim 55
Independent Claim
77 words
A method of tailoring the crystal morphology of a crystalline transistor electrode in an integrated circuit, the method comprising: forming a dielectric layer; depositing nucleation sites on top of the dielectric layer by exposing the dielectric layer to a first set of deposition conditions selected to optimize grain density; and depositing a polycrystalline layer on top of the nucleation sites by exposing the nucleation sites to a second set of deposition conditions selected to optimize grain size.
Claim 56
Independent Claim
77 words
A method of tailoring the crystal morphology of a crystalline transistor electrode in an integrated circuit, the method comprising: forming a dielectric layer; depositing nucleation sites on top of the dielectric layer by exposing the dielectric layer to a first set of deposition conditions selected to optimize grain density; and depositing a polycrystalline layer on top of the nucleation sites by exposing the nucleation sites to a second set of deposition conditions selected to optimize grain size.
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