US5914896A
Expired / Lapsed
US
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Flash memory with high speed erasing structure using thin oxide and thick oxide semiconductor devices
Assignee: Secure Axcess LLC
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Filing: 1997-08-22
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Granted: 1999-06-22
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Expires: 2017-08-22
Abstract
Abstract A flash memory with a high speed erasing structure includes a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline. A wordline decoder is coupled to the wordlines and configured to selectively apply voltages to the wordlines to perform procedures on the flash transistors, where the procedures include a read procedure, an erase procedure and a program procedure. During the erase procedure, the wordline decoder is configured to apply a first increasingly negative voltage in a first voltage range to at least one selected wordline until a first threshold voltage is met, then to apply a second increasingly negative voltage in a second voltage range to the selected wordline and to simultaneously apply a third negative voltage in a third voltage range to at least one deselected wordline. Another embodiment of the invention increases the selected sourceline voltage to achieve a high voltage differential between the gate and source of flash transistors selected to be erased. In another second embodiment, the wordline decoder is constructed from thin oxide and thick oxide semiconductor devices. Thick oxide devices are used in the wordline driver, which allows an increased voltage differential to be applied to the wordlines without damaging the wordline driver. Advantages of the invention include a fast erasing procedure due to the increased voltage differential applied between the gate and source of flash transistors selected to be erased.
Inventors
- 👤 Peter W. Lee
- 👤 Fu-Chang Hsu
- 👤 Hsing-Ya Tsao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:16
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C11/5642; G11C16/08; G11C16/10; G11C16/14; G11C16/16; G11C16/3404; G11C16/3409; G11C16/3431; H; H10; H10B; H10B69/00; G11C16/30; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/564; G11C2211/5642; G11C2211/5645; G11C8/00; G11C8/14
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
141 words
A flash memory comprising: a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline; a wordline decoder having semiconductor devices devices coupled to said wordlines and configured to selectively apply voltages to said wordlines to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein during said erase procedure, said wordline decoder is configured to apply a first increasingly negative selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met, and to apply a decreased deselected voltage decreasing said deselected voltage from one voltage to a more negative voltage to at least one deselected wordline in order to maintain a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 2
Dependent Claim
141 words
A flash memory comprising: a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline; a wordline decoder having semiconductor devices devices coupled to said wordlines and configured to selectively apply voltages to said wordlines to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein during said erase procedure, said wordline decoder is configured to apply a first increasingly negative selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met, and to apply a decreased deselected voltage decreasing said deselected voltage from one voltage to a more negative voltage to at least one deselected wordline in order to maintain a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 3
Dependent Claim
13 words
The flash memory of claim 1, wherein: said erase procedure is approximately linear.
Claim 4
Dependent Claim
101 words
The flash memory of claim 2, wherein: during said erase procedure, said wordline decoder is configured to apply a first increasingly negative voltage in a first voltage range to at least one selected wordline until a first applied voltage is met, then to apply a second increasingly negative voltage in a second voltage range to said selected wordline and to apply said deselected voltage, which is a third negative voltage in a third voltage range to said at least one deselected wordline; said second voltage range is substantially contiguous with said first voltage range; and said erase procedure is approximately linear.
Claim 5
Dependent Claim
30 words
The flash memory of claim 3, wherein: said second voltage range is an adjustable voltage range beyond BVDSS, but wherein said wordline decoder maintains an internal voltage differential below BVDSS.
Claim 6
Dependent Claim
66 words
The flash memory of claim 3, wherein: said flash memory is configured to detect a threshold voltage of at least one of said flash transistors; said first voltage range is applied to said selected wordline when said threshold voltage is above a predetermined threshold voltage; and said second voltage range is applied to said selected wordline when said threshold voltage is below said predetermined threshold voltage.
Claim 7
Dependent Claim
87 words
The flash memory of claim 3, further comprising: a sourceline decoder coupled to said sourceline and configured to selectively apply voltage to said sourceline to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein during said erase procedure, said sourceline decoder is configured to apply a positive voltage; and wherein said sourceline decoder is configured to apply said positive voltage prior to said wordline decoder applying said second increasingly negative voltage in said second voltage range.
Claim 8
Dependent Claim
85 words
The flash memory of claim 3, wherein: a bitline decoder coupled to said bitlines and configured to selectively apply voltages to selected bitlines to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein during said erase procedure, said bitline decoder is configured to apply a positive voltage; and said bitline decoder is configured to apply said positive voltage prior to said wordline decoder applying said second increasingly negative voltage in said second voltage range.
Claim 9
Dependent Claim
59 words
The flash memory of claim 1, further comprising: a sourceline decoder coupled to said sourceline and configured to selectively apply voltage to said sourceline to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein during said erase procedure, said sourceline decoder is configured to apply a positive voltage.
Claim 10
Dependent Claim
22 words
The flash memory of claim 8, wherein: during said erase procedure, said sourceline decoder is configured to apply an increasingly positive voltage.
Claim 11
Dependent Claim
19 words
The flash memory of claim 1, wherein: said first voltage range is an adjustable voltage range beyond +/-10 V.
Claim 12
Dependent Claim
60 words
The flash memory of claim 1, further comprising: a bitline decoder coupled to said bitlines and configured to selectively apply voltages to selected bitlines to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; and wherein during said erase procedure, said bitline decoder is configured to apply a positive voltage.
Claim 13
Dependent Claim
22 words
The flash memory of claim 11, wherein: during said erase procedure, said bitline decoder is configured to apply an increasingly positive voltage.
Claim 14
Dependent Claim
45 words
The flash memory of claim 1, wherein: said flash memory is configured to detect a threshold voltage of at least one of said flash transistors; and said first voltage range is applied to said selected wordline during a first time based on said threshold voltage.
Claim 15
Dependent Claim
140 words
A flash memory comprising: a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline; a wordline decoder having semiconductor devices coupled to said wordlines and configured to selectively apply voltages to said wordlines to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein during said program procedure, said wordline decoder is configured to apply a first increasingly positive selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met, and to apply an increased deselected voltage increasing said deselected voltage from one voltage to a more positive voltage to at least one deselected wordline in order to maintain a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 16
Dependent Claim
140 words
A flash memory comprising: a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline; a wordline decoder having semiconductor devices coupled to said wordlines and configured to selectively apply voltages to said wordlines to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein during said program procedure, said wordline decoder is configured to apply a first increasingly positive selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met, and to apply an increased deselected voltage increasing said deselected voltage from one voltage to a more positive voltage to at least one deselected wordline in order to maintain a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 17
Dependent Claim
100 words
The flash memory of claim 14, wherein: during said program procedure, said wordline decoder is configured to apply a first increasingly positive voltage in a first voltage range to at least one selected wordline until a first applied voltage is met, then to apply a second increasingly positive voltage in a second voltage range to said selected wordline and to apply said deselected voltage, which is a third positive voltage in a third voltage range to at least one deselected wordline; said second voltage range is substantially contiguous with said first voltage range; and said program procedure is approximately linear.
Claim 18
Dependent Claim
66 words
The flash memory of claim 15, wherein: said flash memory is configured to detect a threshold voltage of at least one of said flash transistors; said first voltage range is applied to said selected wordline while said threshold voltage is below a predetermined threshold voltage; and said second voltage range is applied to said selected wordline while said threshold voltage is above said predetermined threshold voltage.
Claim 19
Dependent Claim
45 words
The flash memory of claim 14, wherein: said flash memory is configured to detect a threshold voltage of at least one of said flash transistors; and said first voltage range is applied to said selected wordline during a first time based on said threshold voltage.
Claim 20
Dependent Claim
19 words
The flash memory of claim 14, wherein: said first voltage range is an adjustable voltage range beyond +/-10 V.
Claim 21
Dependent Claim
59 words
The flash memory of claim 14, further comprising: a sourceline decoder coupled to said sourceline and configured to selectively apply voltage to said sourceline to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein during said program procedure, said sourceline decoder is configured to apply a positive voltage.
Claim 22
Dependent Claim
59 words
The flash memory of claim 14, further comprising: a bitline decoder coupled to said bitlines and configured to selectively apply voltages to selected bitlines to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein during said program procedure, said bitline decoder is configured to apply a positive voltage.
Claim 23
Independent Claim
105 words
A method of performing an erase procedure in a flash memory having a bank of flash transistors with a plurality of wordlines, a plurality of bitlines and a sourceline, using a wordline decoder having semiconductor devices, comprising the steps of: applying a first increasingly negative selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met; applying a decreased deselected voltage decreasing said deselected voltage from one voltage to a more negative voltage to at least one deselected wordline; and maintaining a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 24
Independent Claim
105 words
A method of performing an erase procedure in a flash memory having a bank of flash transistors with a plurality of wordlines, a plurality of bitlines and a sourceline, using a wordline decoder having semiconductor devices, comprising the steps of: applying a first increasingly negative selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met; applying a decreased deselected voltage decreasing said deselected voltage from one voltage to a more negative voltage to at least one deselected wordline; and maintaining a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 25
Dependent Claim
12 words
The method of claim 21, wherein: said erase procedure is approximately linear.
Claim 26
Dependent Claim
63 words
The method of claim 21, further comprising the step of: applying a second increasingly negative voltage in a second voltage range to said selected wordline and applying said deselected voltage, which is a third negative voltage in a third voltage range; and wherein said second voltage range is substantially contiguous with said first voltage range; and wherein said erase procedure is approximately linear.
Claim 27
Dependent Claim
66 words
The method of claim 23, further comprising the step of: detecting a threshold voltage of at least one of said flash transistors; and wherein said first voltage range is applied to said selected wordline when said threshold voltage is above a predetermined threshold voltage; and wherein said second voltage range is applied to said selected wordline when said threshold voltage is below said predetermined threshold voltage.
Claim 28
Dependent Claim
17 words
The method of claim 23, wherein: said second voltage range is an adjustable voltage range beyond BVDSS.
Claim 29
Dependent Claim
28 words
The method memory of claim 23, further comprising the step of: selectively applying to a selected sourceline a positive voltage prior to applying said second increasingly negative voltage.
Claim 30
Dependent Claim
28 words
The method memory of claim 23, further comprising the step of: selectively applying to a selected bitline a positive voltage prior to applying said second increasingly negative voltage.
Claim 31
Dependent Claim
20 words
The method memory of claim 21, further comprising the step of: selectively applying to a selected sourceline a positive voltage.
Claim 32
Dependent Claim
21 words
The method memory of claim 21, further comprising the step of: selectively applying to a selected sourceline an increasingly positive voltage.
Claim 33
Dependent Claim
18 words
The method of claim 21, wherein: said second voltage range is an adjustable voltage range beyond +/-10 V.
Claim 34
Dependent Claim
22 words
The method memory of claim 21, further comprising the step of: selectively applying to at least one selected bitline a positive voltage.
Claim 35
Dependent Claim
21 words
The method memory of claim 21, further comprising the step of: selectively applying to a selected bitline an increasingly positive voltage.
Claim 36
Dependent Claim
43 words
The method of claim 21, further comprising the step of: detecting a threshold voltage of at least one of said flash transistors; and wherein said first voltage range is applied to said selected wordline during a first time based on said threshold voltage.
Claim 37
Independent Claim
106 words
A method of performing a program procedure in a flash memory having a bank of flash transistors with a plurality of wordlines, a plurality of bitlines and a sourceline, using a wordline decoder having semiconductor devices, comprising the steps of: applying a first increasingly positive selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met; applying an increased deselected wordline voltage increasing said deselected voltage from one voltage to a more positive voltage to at least one deselected wordline; and maintaining a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 38
Independent Claim
106 words
A method of performing a program procedure in a flash memory having a bank of flash transistors with a plurality of wordlines, a plurality of bitlines and a sourceline, using a wordline decoder having semiconductor devices, comprising the steps of: applying a first increasingly positive selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met; applying an increased deselected wordline voltage increasing said deselected voltage from one voltage to a more positive voltage to at least one deselected wordline; and maintaining a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 39
Dependent Claim
63 words
The method of claim 34, further comprising the step of: applying a second increasingly positive voltage in a second voltage range to said selected wordline and applying said deselected voltage, which is a third negative voltage in a third voltage range; and wherein said second voltage range is substantially contiguous with said first voltage range; and wherein said program procedure is approximately linear.
Claim 40
Dependent Claim
18 words
The method of claim 35, wherein: said second voltage range is an adjustable voltage range beyond +/-10 V.
Claim 41
Dependent Claim
66 words
The method of claim 35, further comprising the step of: detecting a threshold voltage of at least one of said flash transistors; and wherein said first voltage range is applied to said selected wordline while said threshold voltage is below a predetermined threshold voltage; and wherein said second voltage range is applied to said selected wordline while said threshold voltage is above said predetermined threshold voltage.
Claim 42
Dependent Claim
43 words
The method of claim 34, further comprising the step of: detecting a threshold voltage of at least one of said flash transistors; and wherein said first voltage range is applied to said selected wordline during a first time based on said threshold voltage.
Claim 43
Dependent Claim
20 words
The method memory of claim 34, further comprising the step of: selectively applying to a selected sourceline a negative voltage.
Claim 44
Dependent Claim
22 words
The method memory of claim 34, further comprising the step of: selectively applying to at least one selected bitline a negative voltage.
Claim 45
Dependent Claim
235 words
A flash memory comprising: a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline; a wordline decoder having semiconductor devices coupled to said wordlines and configured to selectively apply voltages to said wordlines to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein said wordline decoder executes one of said erase procedure and said program procedure: wherein during said erase procedure, said wordline decoder is configured to apply a first increasingly negative selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met, and to apply a decreased deselected voltage decreasing said deselected voltage from one voltage to a more negative voltage to at least one deselected wordline in order to maintain a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage; and wherein during said program procedure, said wordline decoder is configured to apply a first increasingly positive selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met, and to apply an increased deselected voltage increasing said deselected voltage from one voltage to a more positive voltage to at least one deselected wordline in order to maintain a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 46
Dependent Claim
235 words
A flash memory comprising: a bank of flash transistors having a plurality of wordlines, a plurality of bitlines and a sourceline; a wordline decoder having semiconductor devices coupled to said wordlines and configured to selectively apply voltages to said wordlines to perform procedures on said flash transistors, said procedures including a read procedure, an erase procedure and a program procedure; wherein said wordline decoder executes one of said erase procedure and said program procedure: wherein during said erase procedure, said wordline decoder is configured to apply a first increasingly negative selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met, and to apply a decreased deselected voltage decreasing said deselected voltage from one voltage to a more negative voltage to at least one deselected wordline in order to maintain a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage; and wherein during said program procedure, said wordline decoder is configured to apply a first increasingly positive selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met, and to apply an increased deselected voltage increasing said deselected voltage from one voltage to a more positive voltage to at least one deselected wordline in order to maintain a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 47
Independent Claim
192 words
A method of performing one of an erase procedure and a program procedure in a flash memory having a bank of flash transistors with a plurality of wordlines, a plurality of bitlines and a sourceline, using a wordline decoder having semiconductor devices, comprising the steps of: for the erase procedure: (A) applying a first increasingly negative selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met; (B) applying a decreased deselected voltage decreasing said deselected voltage from one voltage to a more negative voltage to at least one deselected wordline; and (C) maintaining a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage; and for the program procedure: (A) applying a first increasingly positive selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met; (B) applying an increased deselected wordline voltage increasing said deselected voltage from one voltage to a more positive voltage to at least one deselected wordline; and (C) maintaining a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
Claim 48
Independent Claim
192 words
A method of performing one of an erase procedure and a program procedure in a flash memory having a bank of flash transistors with a plurality of wordlines, a plurality of bitlines and a sourceline, using a wordline decoder having semiconductor devices, comprising the steps of: for the erase procedure: (A) applying a first increasingly negative selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met; (B) applying a decreased deselected voltage decreasing said deselected voltage from one voltage to a more negative voltage to at least one deselected wordline; and (C) maintaining a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage; and for the program procedure: (A) applying a first increasingly positive selected voltage in a first voltage range to at least one selected wordline until a first applied voltage is met; (B) applying an increased deselected wordline voltage increasing said deselected voltage from one voltage to a more positive voltage to at least one deselected wordline; and (C) maintaining a voltage difference between said selected voltage and said deselected voltage below a breakdown voltage.
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