US5568419A — Non-volatile semiconductor memory device and data…

Claim 1

Independent Claim 228 words

A non-volatile semiconductor device comprising: a memory cell array having a plurality of memory cells into which data is electrically written and from which data is erased, said memory cells being arranged in a matrix form and each memory cell being connected to a corresponding one of row lines and a corresponding one of column lines; an erasing circuit for flash-erasing data stored in said plurality of memory cells; a selection circuit for selecting one of said memory cells, said selection circuit setting a selected row line to a positive potential and setting non-selected row lines to negative potentials in an overeasing verification mode for detecting an overerased memory cell and a weak program mode for weak programming said overerased memory cell; a detection circuit connected to the column lines, for detecting a voltage read out from the memory cell selected by said selection circuit, said detection circuit comparing a voltage read out from the memory cell with a first reference voltage in an erasing verification mode and comparing a voltage read out from the memory cell with a second reference voltage in said overerasing verification mode; and a weak program circuit for supplying a voltage lower than a normal writing voltage to the overerased memory cell to raise a threshold voltage thereof by a small amount when the overerased memory cell is detected by said detection circuit.

Claim 2

Dependent Claim 228 words

A non-volatile semiconductor device comprising: a memory cell array having a plurality of memory cells into which data is electrically written and from which data is erased, said memory cells being arranged in a matrix form and each memory cell being connected to a corresponding one of row lines and a corresponding one of column lines; an erasing circuit for flash-erasing data stored in said plurality of memory cells; a selection circuit for selecting one of said memory cells, said selection circuit setting a selected row line to a positive potential and setting non-selected row lines to negative potentials in an overeasing verification mode for detecting an overerased memory cell and a weak program mode for weak programming said overerased memory cell; a detection circuit connected to the column lines, for detecting a voltage read out from the memory cell selected by said selection circuit, said detection circuit comparing a voltage read out from the memory cell with a first reference voltage in an erasing verification mode and comparing a voltage read out from the memory cell with a second reference voltage in said overerasing verification mode; and a weak program circuit for supplying a voltage lower than a normal writing voltage to the overerased memory cell to raise a threshold voltage thereof by a small amount when the overerased memory cell is detected by said detection circuit.

Claim 3

Dependent Claim 30 words

A device according to claim 1, wherein said erasing circuit flash-erases data in a plurality of memory cells when an insufficiently erased memory cell is detected by said detection circuit.

Claim 4

Dependent Claim 62 words

A device according to claim 1, wherein the first reference voltage is a voltage which is slightly higher than an upper limit of a threshold voltage of said memory cells in the erased state and the second reference voltage is a voltage which is substantially equal to a lower limit of the threshold voltage of said memory cells in the erased state.

Claim 5

Dependent Claim 159 words

A device according to claim 1, wherein said detection circuit includes: a voltage generating circuit for generating a first voltage at a time of erasing verification and a second voltage different from the first voltage at a time of overerasing verification; a reference cell whose gate is supplied with one of the first and second voltages generated from said voltage generating circuit, said reference cell generating a reference current according to one of the first and second voltages supplied thereto; a first load circuit for generating one of the first and second reference voltages according to the reference current; a second load circuit for generating a voltage corresponding to a cell current flowing in said memory cell, the cell current being set to 1/m (m>1) times the reference current; and a differential amplifier connected to said first and second load circuits, for comparing one of the first and second voltages with a voltage generated by said second load circuit.

Claim 6

Dependent Claim 45 words

A device according to claim 4, wherein said first load circuit is constructed by a first transistor, said second load circuit is constructed by a second transistor, and a mutual conductance of said first transistor is set to m times that of said second transistor.

Claim 7

Dependent Claim 26 words

A device according to claim 4, wherein a mutual conductance of a transistor constructing said reference cell is set smaller than that of said memory cell.

Claim 8

Dependent Claim 29 words

A device according to claim 4, wherein a channel length of a transistor constructing said reference cell is set larger than that of a transistor constructing said memory cell.

Claim 9

Dependent Claim 29 words

A device according to claim 4, wherein a channel width of a transistor constructing said reference cell is set larger than that of a transistor constructing said memory cell.

Claim 10

Dependent Claim 158 words

A device according to claim 1, wherein said detection circuit includes: a voltage generating circuit for generating a first voltage when erasing verification is effected by said detection circuit and generating a second voltage different from the first voltage when overerasing verification is effected by said detection circuit; a reference cell supplied with one of the first and second voltages generated from said voltage generating circuit at a gate thereof, for generating a reference current according to one of the first and second voltages supplied thereto; a first load circuit connected to said reference cell, for generating one of the first and second reference voltages according to the reference current; a second load circuit for generating a voltage corresponding to a cell current flowing in said memory cell; and a differential amplifier connected to said first and second load circuits, for comparing one of the first and second voltages with a voltage generated by said second load circuit.

Claim 11

Dependent Claim 102 words

A device according to claim 9, wherein said voltage generating circuit generates a third voltage which is slightly higher than an upper limit of a threshold voltage of said memory cells in the erased state and supplies the third voltage to the gate of said reference cell when erasing verification is effected by said detection circuit and generates a fourth voltage which is substantially equal to a lower limit of the threshold voltage of said memory cells in the erased state and supplies the fourth voltage to the gate of said reference cell when overerasing verification is effected by said detection circuit.

Claim 12

Dependent Claim 120 words

A device according to claim 9, wherein said voltage generating circuit includes: a transistor whose current path is connected between a first power supply and an output terminal; first and second resistors series-connected between said output terminal and a second power supply; and a differential amplifier having a first input terminal connected to a connection node between said first and second resistors, a second input terminal supplied with a reference voltage and an output terminal connected to a gate of said transistor, the reference voltage being set to a first voltage when erasing verification is effected by said detection circuit and set to a second voltage different from the first voltage when overerasing verification is effected by said detection circuit.

Claim 13

Dependent Claim 42 words

A device according to claim 9, wherein said first load circuit is constructed by a first transistor, said second load circuit is constructed by a second transistor, and mutual conductances of said first and second transistors are set equal to each other.

Claim 14

Dependent Claim 42 words

A device according to claim 1, wherein said selection circuit sets a selected row line to a positive voltage and sets a non-selected row line to a negative voltage at a time of weak program and overerasing verification by said detection circuit.

Claim 15

Dependent Claim 18 words

A device according to claim 1, wherein said memory cell array is divided into a plurality of blocks.

Claim 16

Dependent Claim 30 words

A device according to claim 14, further comprising a block selecting circuit for selecting one of said plurality of blocks, said block selecting circuit being connected to said selection circuit.

Claim 17

Dependent Claim 153 words

An erasing method for a non-volatile semiconductor device including a memory cell army having a plurality of electrically programmable and erasable memory cells arranged in a matrix form, comprising: a first step of flash-erasing data stored in said plurality of memory cells, and then, verifying the data of said memory cells one at a time and repeatedly effecting the flash-erasing operation until all of said memory cells are set into an erased state; a second step of setting a selected row line to a positive voltage, setting a non-selected row line to a negative voltage, and detecting an overerased memory cell for each bit when all of said memory cells are set into the erased state; and a third step of slightly raising the threshold voltage of an overerased memory cell by applying a voltage lower than the normal writing voltage to the overerased memory cell when the overerased memory cell is detected.

Claim 18

Dependent Claim 153 words

An erasing method for a non-volatile semiconductor device including a memory cell army having a plurality of electrically programmable and erasable memory cells arranged in a matrix form, comprising: a first step of flash-erasing data stored in said plurality of memory cells, and then, verifying the data of said memory cells one at a time and repeatedly effecting the flash-erasing operation until all of said memory cells are set into an erased state; a second step of setting a selected row line to a positive voltage, setting a non-selected row line to a negative voltage, and detecting an overerased memory cell for each bit when all of said memory cells are set into the erased state; and a third step of slightly raising the threshold voltage of an overerased memory cell by applying a voltage lower than the normal writing voltage to the overerased memory cell when the overerased memory cell is detected.

Claim 19

Dependent Claim 32 words

A method according to claim 16, wherein the selected row line is set to a positive voltage and the non-selected row line is set to a negative voltage in said first step.

Claim 20

Dependent Claim 36 words

A method according to claim 16, wherein a reference voltage for detection is set slightly higher than an upper limit of a threshold voltage of the memory cells in the erased state in said first step.

Claim 21

Dependent Claim 36 words

A method according to claim 16, wherein a reference voltage for detection is set substantially equal to a lower limit of a threshold voltage of the memory cells in the erased state in said second step.

Claim 22

Dependent Claim 21 words

A method according to claim 16, wherein the non-selected row line is set to a negative voltage in said third step.

Claim 23

Dependent Claim 189 words

An erasing method for a non-volatile semiconductor device including a memory cell array having a plurality of electrically programmable and erasable memory cells arranged in a matrix form, comprising the steps of: flash-erasing data stored in said plurality of memory cells; setting a selected row line to a positive voltage and setting a non-selected row line to a negative voltage after the flash-erasing, and reading data of said memory cells for each bit to detect an insufficiently erased memory cell; effecting the flash-erasing process again when an insufficiently erased memory cell is detected in said detection step; setting a selected row line to a positive voltage and setting a non-selected row line to a negative voltage when all of said memory cells are set into an erased state, and detecting an overerased memory cell for each bit; and setting a selected row line to a positive voltage, setting a non-selected row line to a negative voltage, and applying a voltage lower than the normal writing voltage to an overerased memory cell to slightly raise the threshold voltage of the overerased memory cell when the overerased memory cell is detected.

Claim 24

Dependent Claim 189 words

An erasing method for a non-volatile semiconductor device including a memory cell array having a plurality of electrically programmable and erasable memory cells arranged in a matrix form, comprising the steps of: flash-erasing data stored in said plurality of memory cells; setting a selected row line to a positive voltage and setting a non-selected row line to a negative voltage after the flash-erasing, and reading data of said memory cells for each bit to detect an insufficiently erased memory cell; effecting the flash-erasing process again when an insufficiently erased memory cell is detected in said detection step; setting a selected row line to a positive voltage and setting a non-selected row line to a negative voltage when all of said memory cells are set into an erased state, and detecting an overerased memory cell for each bit; and setting a selected row line to a positive voltage, setting a non-selected row line to a negative voltage, and applying a voltage lower than the normal writing voltage to an overerased memory cell to slightly raise the threshold voltage of the overerased memory cell when the overerased memory cell is detected.

Claim 25

Dependent Claim 40 words

A method according to claim 21, wherein a reference voltage for detection is set slightly higher than an upper limit of a threshold voltage of the memory cells in the erased state when the insufficiently erased memory cell is detected.

Claim 26

Dependent Claim 39 words

A method according to claim 21, wherein a reference voltage for detection is set substantially equal to a lower limit of a threshold voltage of the memory cells in the erased state when the overerased memory cell is detected.

Claim 27

Dependent Claim 215 words

A non-volatile semiconductor device comprising: a memory cell army having a plurality of memory cells into which data is electrically written and from which data is erased, said memory cells being arranged in a matrix form and each memory cell being connected to a corresponding one of row lines and a corresponding one of column lines; an erasing circuit for flash-erasing data stored in said plurality of memory cells; a row decoder having an N-channel transistor, for selecting one of said memory cells, said row decoder setting a selected row line to a positive potential and setting non-selected row lines to negative potentials through said N-channel transistor during an overerasing verification mode for detecting an overerased memory cell and a weak program mode for weak programming said overerased memory cell; a sense amplifier connected to the column line, for detecting a voltage read out from the memory cell selected by said row decoder, said sense amplifier comparing a voltage read out from the memory cell with a reference voltage during said overerasing verification mode; and a weak program circuit for supplying a voltage lower than a normal writing voltage to the overerased memory cell to raise a threshold voltage thereof by a small amount when the overerased memory cell is detected by said detection circuit.

Claim 28

Dependent Claim 215 words

A non-volatile semiconductor device comprising: a memory cell army having a plurality of memory cells into which data is electrically written and from which data is erased, said memory cells being arranged in a matrix form and each memory cell being connected to a corresponding one of row lines and a corresponding one of column lines; an erasing circuit for flash-erasing data stored in said plurality of memory cells; a row decoder having an N-channel transistor, for selecting one of said memory cells, said row decoder setting a selected row line to a positive potential and setting non-selected row lines to negative potentials through said N-channel transistor during an overerasing verification mode for detecting an overerased memory cell and a weak program mode for weak programming said overerased memory cell; a sense amplifier connected to the column line, for detecting a voltage read out from the memory cell selected by said row decoder, said sense amplifier comparing a voltage read out from the memory cell with a reference voltage during said overerasing verification mode; and a weak program circuit for supplying a voltage lower than a normal writing voltage to the overerased memory cell to raise a threshold voltage thereof by a small amount when the overerased memory cell is detected by said detection circuit.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-10-22	2000-04-22	2000-10-22	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-10-22	2004-04-22	2004-10-22	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-10-22	2008-04-22	2008-10-22	$7700.00	Window Closed / Lapsed

Non-volatile semiconductor memory device and data erasing method therefor

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