Patent US6452432B2 successfully refreshed from Google Patents.
US6452432B2
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Signal processing circuits having a pair of delay locked loop (DLL) circuits for adjusting a duty-cycle of a periodic digital signal and methods of operating same
Assignee: Samsung Electronics Co Ltd
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Filing: 2001-03-23
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Granted: 2002-09-17
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Expires: 2021-03-23
Abstract
Abstract A signal processing circuit includes a first delay locked loop (DLL) circuit that generates a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal and a leading edge of a feedback signal and a second DLL circuit that generates a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal. Because the first and second intermediate output signals are based on the phase difference between the reference signal and the leading and trailing edges of a feedback signal, respectively, and the first and second intermediate output signals are not derived from the reference signal, the jitter that may be introduced into the first and second intermediate output signals may be reduced.
Inventors
- 👤 Kyu-hyoun Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:05
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; G11C8/00; G11C8/18; G11C7/10; G11C7/1072; H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565; H03L; H03L7/00; H03L7/06; H03L7/07; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/085; H03L7/087
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
103 words
A signal processing circuit, comprising: a first delay locked loop (DLL) circuit that generates a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; and a second DLL circuit that generates a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals.
Claim 2
Dependent Claim
103 words
A signal processing circuit, comprising: a first delay locked loop (DLL) circuit that generates a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; and a second DLL circuit that generates a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals.
Claim 3
Dependent Claim
30 words
A signal processing circuit as recited in claim 1 , further comprising: a mixer circuit that generates an output signal in response to the first and second intermediate output signals.
Claim 4
Dependent Claim
62 words
A signal processing circuit as recited in claim 2 , wherein the mixer circuit generates a leading edge transition of the output signal in response to a leading edge transition of the first intermediate output signal and the mixer circuit generates a trailing edge transition of the output signal in response to a trailing edge transition of the second intermediate output signal.
Claim 5
Dependent Claim
22 words
A signal processing circuit as recited in claim 2 , wherein the output signal and the feedback signal are the same signal.
Claim 6
Dependent Claim
26 words
A signal processing circuit as recited in claim 2 , further comprising: a delay circuit that generates the feedback signal in response to the output signal.
Claim 7
Dependent Claim
68 words
A signal processing circuit as recited in claim 2 , wherein the mixer circuit comprises: a flip-flop circuit that generates the output signal in response to a set signal and a reset signal; a first logic circuit that generates the set signal in response to the first intermediate output signal; and a second logic circuit that generates the reset signal in response to the second intermediate output signal.
Claim 8
Dependent Claim
27 words
A signal processing circuit as recited in claim 1 , further comprising: a duty-cycle corrector circuit that generates the reference signal in response to the input signal.
Claim 9
Dependent Claim
42 words
A signal processing circuit as recited in claim 1 , wherein the first and second DLL circuits comprise: a delay unit that generates a plurality of delay signals corresponding to delayed versions of the input signal in response to the input signal.
Claim 10
Dependent Claim
103 words
A signal processing circuit as recited in claim 8 , wherein the first DLL circuit further comprises: a first phase comparator circuit that determines the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal in response to the reference signal and the feedback signal; and a first multiplexer that selects a first one of the plurality of delay signals in response to the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal and outputs the first selected delay signal as the first intermediate output signal.
Claim 11
Dependent Claim
67 words
A signal processing circuit as recited in claim 9 , wherein the first DLL circuit further comprises: a first register that latches the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal therein and provides the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal to the first multiplexer.
Claim 12
Dependent Claim
135 words
A signal processing circuit as recited in claim 9 , wherein the second DLL circuit further comprises: a first inverter that generates a complementary reference signal in response to the reference signal; a second inverter that generates a complementary feedback signal in response to the feedback signal; a second phase comparator circuit that determines the phase difference between the trailing edge of the reference signal and the trailing edge of the feedback signal in response to the complementary reference signal and the complementary feedback signal; and a second multiplexer that selects a second one of the plurality of delay signals in response to the phase difference between the trailing edge of the reference signal and the trailing edge of the feedback signal and outputs the second selected delay signal as the second intermediate output signal.
Claim 13
Dependent Claim
67 words
A signal processing circuit as recited in claim 11 , wherein the second DLL circuit further comprises: a second register that latches the phase difference between the trailing edge of the reference signal and the trailing edge of the feedback signal therein and provides the phase difference between the trailing edge of the reference signal and the trailing edge of the feedback signal to the second multiplexer.
Claim 14
Dependent Claim
145 words
An integrated circuit memory device, comprising: a first delay locked loop (DLL) circuit that generates a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; a second DLL circuit that generates a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals; an input receiver circuit that generates processed data in response to input data and the first and second intermediate output signals; and a memory cell array that stores the processed data therein in response to the first and second intermediate output signals.
Claim 15
Dependent Claim
145 words
An integrated circuit memory device, comprising: a first delay locked loop (DLL) circuit that generates a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; a second DLL circuit that generates a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals; an input receiver circuit that generates processed data in response to input data and the first and second intermediate output signals; and a memory cell array that stores the processed data therein in response to the first and second intermediate output signals.
Claim 16
Dependent Claim
31 words
An integrated circuit memory device as recited in claim 13 , further comprising: a mixer circuit that generates an output signal in response to the first and second intermediate output signals.
Claim 17
Dependent Claim
63 words
An integrated circuit memory device as recited in claim 14 , wherein the mixer circuit generates a leading edge transition of the output signal in response to a leading edge transition of the first intermediate output signal and the mixer circuit generates a trailing edge transition of the output signal in response to a trailing edge transition of the second intermediate output signal.
Claim 18
Dependent Claim
30 words
An integrated circuit memory device as recited in claim 14 , wherein the input receiver circuit generates the processed data in response to the input data and the output signal.
Claim 19
Dependent Claim
30 words
An integrated circuit memory device as recited in claim 14 , further comprising: interface logic that couples the processed data from the input receiver circuit to the memory cell array.
Claim 20
Dependent Claim
35 words
An integrated circuit memory device as recited in claim 17 , further comprising: an output buffer that generates output data in response to the data stored in the memory cell array and the output signal.
Claim 21
Independent Claim
92 words
A method of processing a signal, comprising: generating a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; and generating a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals.
Claim 22
Independent Claim
92 words
A method of processing a signal, comprising: generating a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; and generating a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals.
Claim 23
Dependent Claim
24 words
A method as recited in claim 19 , further comprising: generating an output signal in response to the first and second intermediate output signals.
Claim 24
Dependent Claim
68 words
A method as recited in claim 20 , wherein generating the output signal in response to the first and second intermediate output signals comprises: generating a leading transition of the output signal in response to a leading edge transition of the first intermediate output signal; and generating a trailing edge transition of the output signal in response to a trailing edge transition of the second intermediate output signal.
Claim 25
Dependent Claim
20 words
A method as recited in claim 20 , wherein the output signal and the feedback signal are the same signal.
Claim 26
Dependent Claim
22 words
A method as recited in claim 20 , further comprising: generating the feedback signal by applying a delay to the output signal.
Claim 27
Dependent Claim
24 words
A method as recited in claim 19 , further comprising: generating a plurality of delay signals corresponding to delayed versions of the input signal.
Claim 28
Dependent Claim
85 words
A method as recited in claim 24 , wherein generating the first intermediate output signal comprises: determining the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal; selecting a first one of the plurality of delay signals based on the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal; and generating the first intermediate output signal as the selected first one of the plurality of delay signals.
Claim 29
Dependent Claim
86 words
A method as recited in claim 25 , wherein generating the second intermediate output signal comprises: determining the phase difference between the trailing edge of the reference signal and the trailing edge of the feedback signal; selecting a second one of the plurality of delay signals based on the phase difference between the trailing edge of the reference sign al and the trailing edge of the feedback signal; and generating the second intermediate output signal as the selected second one of the plurality of delay signals.
Claim 30
Independent Claim
127 words
A method of operating an integrated circuit memory device, comprising: generating a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; generating a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals; processing input data in response to the first and second intermediate output signals; and storing the processed data in the memory cell array in response to the first and second intermediate output signals.
Claim 31
Independent Claim
127 words
A method of operating an integrated circuit memory device, comprising: generating a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; generating a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals; processing input data in response to the first and second intermediate output signals; and storing the processed data in the memory cell array in response to the first and second intermediate output signals.
Claim 32
Dependent Claim
24 words
A method as recited in claim 27 , further comprising: generating an output signal in response to the first and second intermediate output signals.
Claim 33
Dependent Claim
68 words
A method as recited in claim 28 , wherein generating the output signal in response to the first and second intermediate output signals comprises: generating a leading transition of the output signal in response to a leading edge transition of the first intermediate output signal; and generating a trailing edge transition of the output signal in response to a trailing edge transition of the second intermediate output signal.
Claim 34
Dependent Claim
32 words
A method as recited in claim 28 , wherein processing input data in response to the first and second intermediate output signals comprises: processing input data in response to the output signal.
Claim 35
Dependent Claim
28 words
A method as recited in claim 28 , further comprising: generating output data in response to the data stored in the memory cell array and the output signal.
Claim 36
Dependent Claim
94 words
A signal processing system, comprising: means for generating a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; and means for generating a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals.
Claim 37
Dependent Claim
94 words
A signal processing system, comprising: means for generating a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; and means for generating a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals.
Claim 38
Dependent Claim
28 words
A signal processing system as recited in claim 32 , further comprising: means for generating a plurality of delay signals corresponding to delayed versions of the input signal.
Claim 39
Dependent Claim
96 words
A signal processing system as recited in claim 33 , wherein the means for generating the first intermediate output signal comprises: means for determining the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal; means for selecting a first one of the plurality of delay signals based on the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal; and means for generating the first intermediate output signal as the selected first one of the plurality of delay signals.
Claim 40
Dependent Claim
96 words
A signal processing system as recited in claim 34 , wherein the means ofr generating the second intermediate output signal comprises: means for determining the phase difference between the trailing edge of the reference signal and the trailing edge of the feedback signal; means for selecting a second one of the plurality of delay signals based on the phase difference between the trailing edge of the reference signal and the trailing edge of the feedback signal; and means for generating the second intermediate output signal as the selected second one of the plurality of delay signals.
Claim 41
Dependent Claim
131 words
An integrated circuit memory device, comprising: means for generating a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; means for generating a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals; means for processing input data in response to the first and second intermediate output signals; and means for storing the processed data in the memory cell array in response to the first and second intermediate output signals.
Claim 42
Dependent Claim
131 words
An integrated circuit memory device, comprising: means for generating a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal, which is derived from the input signal, and a leading edge of a feedback signal; means for generating a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal, the feedback signal being derived from the first and second intermediate output signals; means for processing input data in response to the first and second intermediate output signals; and means for storing the processed data in the memory cell array in response to the first and second intermediate output signals.
Claim 43
Dependent Claim
29 words
An integrated circuit memory device as recited in claim 36 , further comprising: means for generating an output signal in response to the first and second intermediate output signals.
Claim 44
Dependent Claim
78 words
An integrated circuit memory device as recited in claim 37 , wherein the means for generating the output signal in response to the first and second intermediate output signals comprises: means for generating a leading transition of the output signal in response to a leading edge transition of the first intermediate output signal; and means for generating a trailing edge transition of the output signal in response to a trailing edge transition of the second intermediate output signal.
Claim 45
Dependent Claim
40 words
An integrated circuit memory device as recited in claim 37 , wherein the means for processing input data in response to the first and second intermediate output signals comprises: means for processing input data in response to the output signal.
Claim 46
Dependent Claim
33 words
An integrated circuit memory device as recited in claim 37 , further comprising: means for generating output data in response to the data stored in the memory cell array and the output signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-16 | 2006-03-18 | 2006-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-16 | 2010-03-18 | 2010-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-16 | 2014-03-18 | 2014-09-17 | $7700.00 | Window Closed / Lapsed |