EP1024599A2
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EP
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Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays
Assignee: Infineon Technologies AG
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Filing: 2000-01-21
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Granted: —
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Expires: 2020-01-21
Abstract
Abstract A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.
Inventors
- 👤 Albert M. Chu
- 👤 John A. Fifield
- 👤 Jason E. Rotella
- 👤 Jean-Marc Dortu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 15:47
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; G; G11; G11C; G11C7/00; G11C7/22; B; B02; B02C; B02C4/00; B02C4/10; B02C4/18; B02C4/20; B02C4/28; B02C4/30; H03L7/0816; H03L7/085; H03L7/095
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
226 words
A circuit, comprising: a receiver for receiving an input train of pulses; and a delay-locked-loop coupled to an output of the receiver, the
delay-locked-loop comprising: a pulse generator responsive to received input train of
pulses produced at the output of the receiver for producing first pulses in
response to the leading edges of the received input train of pulses and
second pulses in response to the trailing edges of received input train of
pulses, the leading edge of the first pulse having the same edge type as the
leading edge of the second pulse; a logic network for combining the first pulses and the
second pulses into a composite input signal comprising the first and second
pulses with the leading edge of the first pulse maintaining the same edge
type; a variable delay line fed by the composite input signal
for producing a composite output train of pulses comprising both the first train
of pulses and the second train of pulses after a selected time delay provided
by the delay line; and wherein the delay-locked-loop is responsive to one of the
first train of pulses;and the second train of pulses in the composite output
train of pulses for selecting the time delay of the variable delay line to produce
such composite output train of pulses with a predetermined phase
relationship with the input train of pulses.
Claim 2
Dependent Claim
46 words
The circuit recited in claim 1 wherein the delay-locked-loop includes
a phase comparator for producing a control signal for the variable delay line in
response to a time difference between pulses in the output train of pulses and
pulses in the received train of input pulses.
Claim 3
Dependent Claim
65 words
The circuit recited in claim 2 wherein the delay-locked-loop includes
a logic network for enabling only one of the first and second pulses to pass from
the receiver to the delay line until the phase comparator provides an indication
that the output train of pulses have rising edge types timed coincident with both
the rising and falling edge types of the input train of pulses.
Claim 4
Dependent Claim
115 words
The circuit recited in claim 3 wherein the phase comparator
includes a first input fed by pulses in the output train of pulses and a second
input fed by pulses in the received train of input pulses and wherein the delay-locked-loop includes: a gate fed by the output train of pulses and a gating signal; and a gate pulse generator responsive to one of the first and second
pulses for producing the gating signal during the first pulse to enable the output
train of pulses to pass through such gate to the phase comparator and to inhibit
the output train of pulses from passing through the gate to the phase comparator
during the second pulse.
Claim 5
Dependent Claim
115 words
The circuit recited in claim 2 wherein the phase comparator
includes a first input fed by pulses in the output train of pulses and a second
input fed by pulses in the received train of input pulses and wherein the delay-locked-loop includes: a gate fed by the output train of pulses and a gating signal; and a gate pulse generator responsive to one of the first and second
pulses for producing the gating signal during the first pulse to enable the output
train of pulses to pass through such gate to the phase comparator and to inhibit
the output train of pulses from passing through the gate to the phase comparator
during the second pulse.
Claim 6
Dependent Claim
212 words
A circuit, comprising: a receiver for receiving an input train of pulses; a pulse generating circuit coupled to an output of the
receiver for producing a first pulse in response to a leading edge of each one of
the pulses in the input train of pulses and a second pulse in response to the
trailing edge of each one of the pulses in the input train of pulses, the leading
edges of the first and second pulses having the same edge type; a variable delay line responsive to the first and second
pulses for producing corresponding first and second output pulses, each one of
such first and second output pulses being produced in response to the
corresponding one of the first and second pulses after a time delay selected in
accordance with a control signal fed to the variable delay line; a phase comparator having a first input fed by one of the
first and second pulses and a second input fed by the corresponding one of the
first and second output pulses, for producing the control signal, such control
signal selecting the time delay for the variable delay line to produce the output
pulses with leading edges timed coincident with leading edges of the pulses in
the input train of pulses.
Claim 7
Dependent Claim
56 words
The circuit recited in claim 6 including: a logic network for enabling only one of the first and second
pulses to pass from the receiver to the delay line until the phase comparator
provides an indication that the output train of pulses have leading edges timed
coincident with leading edges of the input train of pulses.
Claim 8
Dependent Claim
112 words
The circuit recited in claim 7 wherein the phase comparator
includes a first input fed by pulses in the output train of pulses and a second
input fed by pulses in the received train of input pulses and including: a gate fed by the output train of pulses and a gating signal; and a gate pulse generator responsive to one of the first and second
pulses for producing the gating signal during the first pulse to enable the output
train of pulses to pass through such gate to the phase comparator and to inhibit
the output train of pulses from passing through the gate to the phase comparator
during the second pulse.
Claim 9
Dependent Claim
112 words
The circuit recited in claim 6 wherein the phase comparator
includes a first input fed by pulses in the output train of pulses and a second
input fed by pulses in the received train of input pulses and including: a gate fed by the output train of pulses and a gating signal; and a gate pulse generator responsive to one of the first and second
pulses for producing the gating signal during the first pulse to enable the output
train of pulses to pass through such gate to the phase comparator and to inhibit
the output train of pulses from passing through the gate to the phase comparator
during the second pulse.
Claim 10
Dependent Claim
358 words
A circuit, comprising: a receiver for receiving an input train of pulses such train
of pulses having a period, T, such receiver providing a first time delay, Δ 1 to the
pulses in the input train of pulses; a pulse generating circuit coupled to an output of the
receiver for producing a first pulse in response to a leading edge of each one of
the pulses in the input train of pulses and a second pulse in response to a trailing
edge of each one of the pulses in the input train of pulses, the leading edges of
the first and second pulses having the same edge type, such pulse generating
circuit producing the first pulses and the second pulses with a second time delay
Δ 2 after the leading edge of pulses in the input train of pulses; a logic network for combining the first pulses and the
second pulses into a composite input signal comprising the first and second
pulses with the leading edge of the first pulse maintaining the same edge type,
such logic network providing a third time delay Δ 3 to the first and second pulses; a variable delay line responsive to the first and second
pulses for producing corresponding first and second output pulses, each one of
such first and second output pulses being produced in response to the
corresponding one of the first and second pulses after a time delay Δ L selected
in accordance with a control signal fed to the variable delay line; a delay network fed by the output train of pulses such
delay network providing a fourth time delay Δ 4 related to Δ 1 +Δ 2 ; a phase comparator having a first input fed by one of the
first and second pulses and a second input coupled to an output of the delay
network, for producing the control signal, such control signal selecting the time
delay Δ L equal to nT-(Δ 1 +Δ 2 +Δ 3 ) , where n is an integer to produce the output
pulses having leading edges timed coincident with leading edges of the pulses in
the input train of pulses.
Claim 11
Dependent Claim
112 words
The circuit recited in claim 10 wherein the phase comparator
includes a first input fed by pulses in the output train of pulses and a second
input fed by pulses in the received train of input pulses and including: a gate fed by the output train of pulses and a gating signal; and a gate pulse generator responsive to one of the first and second
pulses for producing the gating signal during the first pulse to enable the output
train of pulses to pass through such gate to the phase comparator and to inhibit
the output train of pulses from passing through the gate to the phase comparator
during the second pulse.
Claim 12
Independent Claim
101 words
A method for generating a train of output pulses having a
predetermined phase relationship with a train of input pulses, comprising: passing the input train of pulses through a receiver; producing a first pulse in response to the leading edge of each the
received input train of pulses and a second pulse in response to the trailing edge
of each one of the received input train of pulses, each one of the first and
second pulses having leading edges with the same edge type; feeding the first and second pulses through a delay line to
produce the output train of pulses.
Claim 13
Dependent Claim
43 words
The method recited in claim 12 wherein the producing step
includes producing a control signal for the variable delay line in response to a
time difference between pulses in the output train of pulses and pulses in the
received train of input pulses.
Claim 14
Dependent Claim
55 words
The method recited in claim 13 wherein the producing step
comprises enabling only one of the first and second pulses to pass from the
receiver to the delay line until an indication is provided that the output train of
pulses have leading edges timed coincident with the leading edges of the input
train of pulses.
References Cited (Backward Citations)
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