Substrate having specific pad distribution

Claim 2

A substrate for use in packaging of a semiconductor chip, the substrate having opposing upper and lower surfaces, wherein: the upper surface of the substrate comprises a die covering area, a ground ring and a power ring; and the lower surface of the substrate comprises a plurality of first contact pads right under the vicinity of the ground ring and the power ring and a plurality of second contact pads surrounding the first contact pads; wherein the first contact pads are divided into a first group electrically connected to the ground ring and a second group electrically connected to the power ring, wherein the first group pads and the second group pads are arranged alternately, said substrate further comprising a plurality of third contact pads provided at a corresponding position of the lower surface of the substrate under the die covering area, each of the third contact pads being separated from each other by a first distance, all of the third contact pads being separated from the periphery of the die covering area by at least a second distance which is larger than the first distance and said substrate further comprising a plurality of dummy pads which are not coupled to the semiconductor chip on the lower surface of the substrate at a position right under the periphery of the die covering area.

Claim 3

A substrate for use in packaging of a semiconductor chip, the substrate having opposing upper and lower surfaces, wherein: the upper surface of the substrate comprises a die covering area, a ground ring and a power ring; and the lower surface of the substrate comprises a plurality of first contact pads right under the vicinity of the ground ring and the power ring and a plurality of second contact pads surrounding the first contact pads; wherein the first contact pads are divided into a first group electrically connected to the ground ring and a second group electrically connected to the power ring, wherein the first group pads and the second group pads are arranged alternately, and said substrate further comprising a plurality of dummy pads which are not coupled to the semiconductor chip on the lower surface of the substrate at a position right under the periphery of the die covering area.

Claim 4

A substrate for use in packaging of a semiconductor chip, the substrate having opposing upper and lower surfaces, wherein: the upper surface of the substrate comprises a die covering area, a ground ring and a power ring; and the lower surface of the substrate comprises a plurality of first contact pads right under the vicinity of the ground ring and the power ring and a plurality of second contact pads surrounding the first contact pads; wherein the first contact pads are divided into a first group electrically connected to the ground ring and a second group electrically connected to the power ring, wherein the first group pads and the second group pads are arranged alternately, and said substrate further comprising a plurality of dummy pads which are not coupled to the semiconductor chip on the lower surface of the substrate at a position right under the periphery of the die covering area.

Claim 5

A ball grid array package, comprising: a substrate having opposing upper and lower surfaces, the upper surface of the substrate comprising a die covering area, a ground ring and a power ring, the lower surface of the substrate comprising a plurality of first contact pads right under the vicinity of the ground ring and the power ring and a plurality of second contact pads surrounding the first contact pads wherein the first contact pads are divided into a first group electrically connected to the ground ring and a second group electrically connected to the power ring, wherein the first group pads and the second group pads are arranged alternately; a plurality of solder balls attached to the pads of the substrate; a semiconductor chip that is mounted to die covering area on the upper surface of the substrate and electrically coupled to the substrate; a plurality of third contact pads provided at a corresponding position of the lower surface of the substrate under the die covering area, each of the third contact pads being separated from each other by a first distance, all of the third contact pads being separated from the periphery of the die covering area by at least a second distance which is larger than the first distance; and a plurality of dummy pads which are not coupled to the semiconductor chip on the lower surface of the substrate at a position right under the periphery of the die covering area.

Claim 6

A ball grid array package, comprising: a substrate having opposing upper and lower surfaces, the upper surface of the substrate comprising a die covering area, a ground ring and a power ring, the lower surface of the substrate comprising a plurality of first contact pads right under the vicinity of the ground ring and the power ring and a plurality of second contact pads surrounding the first contact pads wherein the first contact pads are divided into a first group electrically connected to the ground ring and a second group electrically connected to the power ring, wherein the first group pads and the second group pads are arranged alternately; a plurality of solder balls attached to the pads of the substrate; a semiconductor chip that is mounted to die covering area on the upper surface of the substrate and electrically coupled to the substrate; a plurality of third contact pads provided at a corresponding position of the lower surface of the substrate under the die covering area, each of the third contact pads being separated from each other by a first distance, all of the third contact pads being separated from the periphery of the die covering area by at least a second distance which is larger than the first distance; and a plurality of dummy pads which are not coupled to the semiconductor chip on the lower surface of the substrate at a position right under the periphery of the die covering area.

Claim 7

A ball grid array package, comprising: a substrate having opposing upper and lower surfaces, the upper surface of the substrate comprising a die covering area, a ground ring and a power ring, the lower surface of the substrate comprising a plurality of first contact pads right under the vicinity of the ground ring and the power ring and a plurality of second contact pads surrounding the first contact pads wherein the first contact pads are divided into a first group electrically connected to the ground ring and a second group electrically connected to the power ring, wherein the first group pads and the second group pads are arranged alternately; a plurality of solder balls attached to the pads of the substrate; a semiconductor chip that is mounted to die covering area on the upper surface of the substrate and electrically coupled to the substrate; and a plurality of dummy pads which are not coupled to the semiconductor chip on the lower surface of the substrate at a position right under the periphery of the die covering area.

Claim 8

A ball grid array package, comprising: a substrate having opposing upper and lower surfaces, the upper surface of the substrate comprising a die covering area, a ground ring and a power ring, the lower surface of the substrate comprising a plurality of first contact pads right under the vicinity of the ground ring and the power ring and a plurality of second contact pads surrounding the first contact pads wherein the first contact pads are divided into a first group electrically connected to the ground ring and a second group electrically connected to the power ring, wherein the first group pads and the second group pads are arranged alternately; a plurality of solder balls attached to the pads of the substrate; a semiconductor chip that is mounted to die covering area on the upper surface of the substrate and electrically coupled to the substrate; and a plurality of dummy pads which are not coupled to the semiconductor chip on the lower surface of the substrate at a position right under the periphery of the die covering area.