Substrate interconnect allowing personalization using spot surface links

Claim 2

A universal interconnect substrate, comprising: a plurality of regularly spaced interconnect cells, each said interconnection cell comprising: a first intermediate layer comprising a plurality of substantially parallel X-conductors substantially extending the length of said cell; a second intermediate layer comprising a plurality of substantially parallel Y-conductors substantially extending the width of said cell; and a surface layer configured above said first intermediate layer and said second intermediate layer, said surface layer comprising: i. a plurality of substantially equally spaced bonding pads configured about the outer boundary of each said cell, wherein the spacing between cells is such that the bonding pad spacing is continuous from cell to cell; ii. a plurality of corner-turning connectors converging inward from said bonding pads, each connector spaced substantially equal distance from adjacent said connector; iii. programming means for selectively connecting said X-conductors and said Y-conductors to said bonding pads; and iv. means for connecting said bonding pads to at least one electrical component placeable upon said surface layer, wherein said programming means comprises: a grounding layer; a plurality of power buses arranged on said first and second intermediate layers; a plurality of continuation vias extending vertically downward from said surface layer to the terminal ends of said X- or Y-conductors; a plurality of corner-turning vias extending downward from said surface layer to an intermediate point of said X- or Y-conductors; a plurality of power vias extending vertically downward from said surface layer to said power buses; a plurality of ground vias extending downward from said surface layer to said grounding layer; and a plurality of programmable conductive links, each conductive link having fixed geometry and placed on said surface layer for selectively connecting said continuation vias, said corner-turning vias, said bonding pads to said power and ground vias, and said bonding pads to said corner-turning connectors.

Claim 3

The universal interconnect substrate of claim 1, said conductive links being short with respect to said X-or Y-conductors.

Claim 4

The universal interconnect substrate of claim 1, said conductive links electrically connecting said continuation vias.

Claim 5

The universal interconnect substrate of claim 1, said conductive links electrically connecting said corner-turning vias.

Claim 6

The universal interconnect substrate of claim 1, said X-conductors and said Y-conductors being substantially orthogonal to one another forming non-interrupted cross-over points near said corner-turning vias.

Claim 7

The universal interconnect substrate of claim 1, said conductive links being short relative to said X- of Y-conductors.

Claim 8

The universal interconnect substrate of claim 1, said conductive links electrically connecting said continuation vias.

Claim 9

A universal interconnect substrate, comprising: a plurality of regularly spaced interconnect cells, each said interconnecting cell comprising: a first intermediate layer comprising a plurality of substantially parallel X-conductors substantially extending the length of said cell; a second intermediate layer comprising a plurality of substantially parallel Y-conductors substantially extending the width of said cell, said X-conductors and said Y-conductors being orthogonal to one another forming non-interrupted cross-over points; and a surface layer configured above said first intermediate layer and said second intermediate layer, said surface layer comprising: i. a plurality of substantially equally spaced bonding pads configured about the outer boundary of each said cell, wherein the spacing between cells is such that the bonding pad spacing is continuous from cell to cell; ii. a plurality of corner-turning connectors converging inward from said bonding pads, each connector spaced substantially equal distance from adjacent said connector; iii. programming means for selectively connecting said X-conductors and said Y-conductors to said bonding pads; and iv. means for connecting said bonding pads to at least one electrical component placeable upon said surface layer.

Claim 10

A universal interconnect substrate, comprising: a plurality of regularly spaced interconnect cells, each said interconnecting cell comprising: a first intermediate layer comprising a plurality of substantially parallel X-conductors substantially extending the length of said cell; a second intermediate layer comprising a plurality of substantially parallel Y-conductors substantially extending the width of said cell, said X-conductors and said Y-conductors being orthogonal to one another forming non-interrupted cross-over points; and a surface layer configured above said first intermediate layer and said second intermediate layer, said surface layer comprising: i. a plurality of substantially equally spaced bonding pads configured about the outer boundary of each said cell, wherein the spacing between cells is such that the bonding pad spacing is continuous from cell to cell; ii. a plurality of corner-turning connectors converging inward from said bonding pads, each connector spaced substantially equal distance from adjacent said connector; iii. programming means for selectively connecting said X-conductors and said Y-conductors to said bonding pads; and iv. means for connecting said bonding pads to at least one electrical component placeable upon said surface layer.

Claim 11

A universal interconnect substrate, comprising: a plurality of substantially square interconnect cells configured side-by-side and spaced equal distance from one another, each said interconnect cell comprising: a grounding layer comprising a substantially planar conductive element; a first interconnect layer comprising a plurality of substantially parallel X-conductors substantially extending the length of said cell; a second interconnect layer comprising a plurality of substantially parallel Y-conductors substantially extending the width of said cells; a power layer comprising a substantially planar conductive element; and, a surface layer configured above said grounding layer, said first intermediate layer and said second intermediate layer, said surface layer comprising: i. a plurality of equally spaced bonding pads configured about the outer boundary of each said cell, wherein the spacing between cells is such that the bonding pad spacing is continuous from cell to cell; ii. a plurality of corner-turning connectors converging inward from said bonding lead pads, each corner-turning connector spaced equal distance from adjacent said corner-turning connector; iii. programming means for selectively connecting said X-conductors, said Y-conductors, said grounding layer, and said power buses to said bonding pads; iv. means for connecting said bonding pads to at least one electrical component placeable upon said surface layer; and, a pair of connector bonding pads placed on said surface layer between each cell and substantially collinear with said bonding pads such that the spacing between said connector bonding pad and adjacent said bonding pads equals the distance between bonding pads.

Claim 12

A universal interconnect substrate, comprising: a plurality of substantially square interconnect cells configured side-by-side and spaced equal distance from one another, each said interconnect cell comprising: a grounding layer comprising a substantially planar conductive element; a first interconnect layer comprising a plurality of substantially parallel X-conductors substantially extending the length of said cell; a second interconnect layer comprising a plurality of substantially parallel Y-conductors substantially extending the width of said cells; a power layer comprising a substantially planar conductive element; and, a surface layer configured above said grounding layer, said first intermediate layer and said second intermediate layer, said surface layer comprising: i. a plurality of equally spaced bonding pads configured about the outer boundary of each said cell, wherein the spacing between cells is such that the bonding pad spacing is continuous from cell to cell; ii. a plurality of corner-turning connectors converging inward from said bonding lead pads, each corner-turning connector spaced equal distance from adjacent said corner-turning connector; iii. programming means for selectively connecting said X-conductors, said Y-conductors, said grounding layer, and said power buses to said bonding pads; iv. means for connecting said bonding pads to at least one electrical component placeable upon said surface layer; and, a pair of connector bonding pads placed on said surface layer between each cell and substantially collinear with said bonding pads such that the spacing between said connector bonding pad and adjacent said bonding pads equals the distance between bonding pads.

Claim 13

The universal interconnect substrate of claim 9, said programming means comprising: a plurality of continuation vias extending substantially vertically downward from said surface layer to the terminal ends of said X- or Y-conductors; a plurality of corner-turning vias extending substantially vertically downward from said surface layer to an intermediate point of said X- or Y-conductors; a plurality of power and ground vias extending substantially vertically downward from said surface layer to said power layer or said grounding layer; a plurality of substantially collinear channel-hop buses extending between the outer edge of said bonding pads and said continuation vias; and a plurality of programmable conductive links, each conductive link having substantially uniform geometry and placed on said surface layer for selectively connecting said continuation vias, said corner-turning vias, said bonding pads to said power and ground vias, said connector bonding pads to said connector buses, said channel-hop buses and said bonding pads to said corner-turning connectors.

Claim 14

The universal interconnect substrate of claim 9, said conductive links electrically connecting said corner-turning vias.

Claim 15

A customizable circuit comprising: a universal interconnect substrate having a plurality of interconnect cells placed side-by-side and equally spaced apart, each interconnecting cell comprising: a grounding layer comprising a planar conductive element; a first intermediate layer comprising a plurality of substantially parallel X-conductors and power buses substantially extending the length of said cell; a second intermediate layer comprising a plurality of substantially parallel Y-conductors and power buses substantially extending the width of said cell, said C-conductors and said Y-conductors overlapping and crossing at a plurality of crossing points; a plurality of continuation vias formed at the terminal ends of each said X-conductors and said Y-conductors; a plurality of pairs of corner-turning vias formed near said plurality of crossing points; and, a surface layer comprising: a plurality of bonding pads surrounding each said interconnect cell; a plurality of corner-turning connectors converging inward from said bonding pads, each corner-turning connector spaced substantially equal distance from said adjacent corner-turning connector; and, programming means for selectively connecting: i. said bonding pads to said corner-turning connectors; ii. said corner-turning connectors to said pairs of corner-turning vias, whereby said corner-turning connectors are selectively connected to either X- or Y-conductors; iii. said continuation vias of each said interconnect cell to continuation vias on adjacent said interconnect cells; iv. said pairs of corner-turning vias; and, at least one electrical component bonded to a selected set of said plurality of bonding pads.

Claim 16

A customizable circuit comprising: a universal interconnect substrate having a plurality of interconnect cells placed side-by-side and equally spaced apart, each interconnecting cell comprising: a grounding layer comprising a planar conductive element; a first intermediate layer comprising a plurality of substantially parallel X-conductors and power buses substantially extending the length of said cell; a second intermediate layer comprising a plurality of substantially parallel Y-conductors and power buses substantially extending the width of said cell, said C-conductors and said Y-conductors overlapping and crossing at a plurality of crossing points; a plurality of continuation vias formed at the terminal ends of each said X-conductors and said Y-conductors; a plurality of pairs of corner-turning vias formed near said plurality of crossing points; and, a surface layer comprising: a plurality of bonding pads surrounding each said interconnect cell; a plurality of corner-turning connectors converging inward from said bonding pads, each corner-turning connector spaced substantially equal distance from said adjacent corner-turning connector; and, programming means for selectively connecting: i. said bonding pads to said corner-turning connectors; ii. said corner-turning connectors to said pairs of corner-turning vias, whereby said corner-turning connectors are selectively connected to either X- or Y-conductors; iii. said continuation vias of each said interconnect cell to continuation vias on adjacent said interconnect cells; iv. said pairs of corner-turning vias; and, at least one electrical component bonded to a selected set of said plurality of bonding pads.

Claim 17

The customizable circuit of claim 12, at least one said electrical component having larger area than said interconnect cell.

Claim 18

The customizable circuit of claim 12, said X-conductors and said Y-conductors being substantially orthogonal to one another forming non-interrupted cross-over points near said corner-turning vias.

Claim 19

The customizable circuit of claim 12, said programming means comprising a plurality of programmable conductive links, each conductive link having substantially uniform geometry placed on said surface layer.

Claim 20

The customizable circuit of claim 12, the universal interconnect substrate further comprising a plurality of power and ground vias placed along the outer boundaries of each said interconnects cell interspersed between a plurality of said bonding pads configured to provide each bonding pad with access to either said power buses or said ground layer.

Claim 21

The customizable circuit of claim 12, the universal interconnect substrate further comprising an insulating medium for electrically isolating said surface layer, said first intermediate layer, said second intermediate layer, and said ground layer.

Claim 22

A customizable circuit of claim 12, said electrical component being configured above at least one of said interconnect cells, said interconnect cells being aligned such that the spacing between the bonding pads of adjacent interconnect cells is equal to the spacing between bonding pads within each interconnect cell.

Claim 23

A customizable circuit comprising: a universal interconnect substrate having a plurality of substantially square interconnect cells configured side-by-side and spaced substantially equal distance from one another, each said interconnect cell comprising: a grounding layer comprising a substantially planar conductive element; a first intermediate layer comprising a plurality of substantially parallel coplanar X-conductors horizontally extending substantially the entire length of said interconnect cell, each said X-conductor being electrically insulated from adjacent said X-conductors within said substrate; a second intermediate layer comprising a plurality of substantially parallel coplanar Y-conductors vertically extending substantially the entire width of said interconnect cell, said Y-conductors and said X-conductors crossing substantially orthogonally at a plurality of crossing points, each said Y-conductor being electrically insulated from adjacent said Y-conductors and from said X-conductors within said substrate; a plurality of substantially horizontal power conductors placed on said first intermediate layer extending the entire length of said interconnect cell and being electrically insulated from said X-conductors and said Y-conductors; a plurality of vertical power conductors placed on said second intermediate layer extending the entire length of said interconnect cell and being electrically isolated from said X-conductors and said Y-conductors; a plurality of continuation vias formed at the terminal ends of each said X-conductor and said Y-conductor; a plurality of pairs of corner-turning vias formed near said plurality of crossing points; a plurality of power and ground vias; and, a programmable surface layer placed above said first and said second intermediate layer, said programmable surface layer comprising: a plurality of equally spaced bonding pads configured about the outer boundary of each said interconnect cell, wherein the spacing between cells is such that the bonding pad spacing is continuous from cell to cell; a plurality of corner-turning connectors converging inward from said bonding pads, each corner-turning connector being spaced substantially equal distance from said adjacent corner-turning connector; a plurality of channel-hop buses configured between said interconnect cells; a pair of connector bonding pads placed on said surface layer between each cell and substantially collinear with said bonding pads such that the spacing between said connector bonding pad and adjacent said bonding pads substantially equals the distance between bonding pads; and, programming means for selectively connecting: i. said bonding pads to said shaped connectors; ii. said corner-turning connectors to said pairs of corner-turning vias; iii. said continuation vias of said inter-connect cell to continuation vias on adjacent said interconnect cells; iv. said pairs of secondary junctions; v. said bonding pads to said power and ground vias, whereby said bonding pads are selectively connected to either power buses or ground layer buses; vi. said connector bonding pads to said connector buses; vii. said channel-hop buses; viii. said channel-hop buses to said continuation vias; and, an electrical component bonded to the top of said universal interconnect substrate, said electrical component having bonding surface connectable to said plurality of bonding pads.

Claim 24

A customizable circuit comprising: a universal interconnect substrate having a plurality of substantially square interconnect cells configured side-by-side and spaced substantially equal distance from one another, each said interconnect cell comprising: a grounding layer comprising a substantially planar conductive element; a first intermediate layer comprising a plurality of substantially parallel coplanar X-conductors horizontally extending substantially the entire length of said interconnect cell, each said X-conductor being electrically insulated from adjacent said X-conductors within said substrate; a second intermediate layer comprising a plurality of substantially parallel coplanar Y-conductors vertically extending substantially the entire width of said interconnect cell, said Y-conductors and said X-conductors crossing substantially orthogonally at a plurality of crossing points, each said Y-conductor being electrically insulated from adjacent said Y-conductors and from said X-conductors within said substrate; a plurality of substantially horizontal power conductors placed on said first intermediate layer extending the entire length of said interconnect cell and being electrically insulated from said X-conductors and said Y-conductors; a plurality of vertical power conductors placed on said second intermediate layer extending the entire length of said interconnect cell and being electrically isolated from said X-conductors and said Y-conductors; a plurality of continuation vias formed at the terminal ends of each said X-conductor and said Y-conductor; a plurality of pairs of corner-turning vias formed near said plurality of crossing points; a plurality of power and ground vias; and, a programmable surface layer placed above said first and said second intermediate layer, said programmable surface layer comprising: a plurality of equally spaced bonding pads configured about the outer boundary of each said interconnect cell, wherein the spacing between cells is such that the bonding pad spacing is continuous from cell to cell; a plurality of corner-turning connectors converging inward from said bonding pads, each corner-turning connector being spaced substantially equal distance from said adjacent corner-turning connector; a plurality of channel-hop buses configured between said interconnect cells; a pair of connector bonding pads placed on said surface layer between each cell and substantially collinear with said bonding pads such that the spacing between said connector bonding pad and adjacent said bonding pads substantially equals the distance between bonding pads; and, programming means for selectively connecting: i. said bonding pads to said shaped connectors; ii. said corner-turning connectors to said pairs of corner-turning vias; iii. said continuation vias of said inter-connect cell to continuation vias on adjacent said interconnect cells; iv. said pairs of secondary junctions; v. said bonding pads to said power and ground vias, whereby said bonding pads are selectively connected to either power buses or ground layer buses; vi. said connector bonding pads to said connector buses; vii. said channel-hop buses; viii. said channel-hop buses to said continuation vias; and, an electrical component bonded to the top of said universal interconnect substrate, said electrical component having bonding surface connectable to said plurality of bonding pads.

Claim 25

The customizable circuit of claim 19, at least one said electrical component having larger area than each said interconnect cell.

Claim 26

The customizable circuit of claim 19, said programming means having conductive links that are short relative to said X- and Y-conductors.

Claim 27

The customizable circuit of claim 19, said programming means having conductive spot links connecting said continuation vias.

Claim 28

The customizable circuit of claim 19, said programming means having conductive spot link-s connecting said corner-turning vias.

Claim 29

The customizable circuit of claim 19, said programming means having a conductive link, each said conductive link having a length-to-width ratio less than 3.

Claim 30

A universal interconnect substrate, comprising: a plurality of regularly spaced interconnect cells, each said interconnecting cell comprising: a first intermediate layer comprising a plurality of substantially parallel X-conductors substantially extending the length of said cell; a second intermediate layer comprising a plurality of substantially parallel Y-conductors substantially extending the width of said cell; said X-conductors and said Y-conductors being orthogonal to one another forming non-interrupted cross-over points; and a surface layer configured above said first intermediate layer and said second intermediate layer, said surface layer comprising: i. a plurality of substantially equally spaced bonding pads configured about the outer boundary of each said cell, wherein the spacing between cells is such that the bonding pad spacing is continuous from cell to cell; ii. a plurality of corner-turning connectors converging inward from said bonding pads, each connector spaced substantially equal distance from adjacent said connector; iii. conductive links for selectively connecting said X-conductors and said Y-conductors to said bonding pads; and wherein iv. said bonding pads are capable of being connected to at lest one electrical component placeable upon said surface layer.

Claim 31

A universal interconnect substrate, comprising: a plurality of regularly spaced interconnect cells, each said interconnecting cell comprising: a first intermediate layer comprising a plurality of substantially parallel X-conductors substantially extending the length of said cell; a second intermediate layer comprising a plurality of substantially parallel Y-conductors substantially extending the width of said cell; said X-conductors and said Y-conductors being orthogonal to one another forming non-interrupted cross-over points; and a surface layer configured above said first intermediate layer and said second intermediate layer, said surface layer comprising: i. a plurality of substantially equally spaced bonding pads configured about the outer boundary of each said cell, wherein the spacing between cells is such that the bonding pad spacing is continuous from cell to cell; ii. a plurality of corner-turning connectors converging inward from said bonding pads, each connector spaced substantially equal distance from adjacent said connector; iii. conductive links for selectively connecting said X-conductors and said Y-conductors to said bonding pads; and wherein iv. said bonding pads are capable of being connected to at lest one electrical component placeable upon said surface layer.

Claim 32

The universal interconnect substrate of claim 25, further comprising: at least one continuation via extending from said surface layer to said X- and Y-conductors; and at lest one corner-turning via extending from said surface layer to said X- and Y-conductors; and wherein said conductive links having a geometry capable of being programmably placed abutting said at least one continuation via and said at least one corner-turning via for selectively connecting said at least one electrical component to said X- and Y-conductors.

Claim 33

The universal interconnect substrate of claim 25, further comprising: an underlying power bus in said substrate; an underlying grounding layer in said substrate; at least one power via extending from said surface layer to said at least one underlying power bus; and at least one ground via extending from said surface layer to said at least one underlying grounding layer; and wherein said conductive links having a geometry capable of being programmably placed abutting said at least one power via and said at least one ground via for selectively connecting said at least one electrical component to said at least one power bus and said at least one grounding layer.

Claim 34

A universal interconnect substrate, comprising: a plurality of regularly spaced interconnect cells, each said interconnecting cell comprising: a first intermediate layer comprising a plurality of substantially parallel X-conductors substantially extending the length of said cell; a second intermediate layer comprising a plurality of substantially parallel Y-conductors substantially extending the width of said cell; said X-conductors and said Y-conductors being orthogonal to one another forming non-interrupted cross-over points; and a surface layer configured above said first intermediate layer and said second intermediate layer, said surface layer comprising: i. a plurality of substantially equally spaced bonding pads configured about the outer boundary of each said cell, wherein the spacing between cells is such tat the bonding pad spacing is continuous from cell to cell; ii. a plurality of corner-turning connectors converging inward from said bonding pads, each connector spaced substantially equal distance from adjacent said connector; and wherein iii. said X-conductors and said Y-conductors are capable of being selectively connected to said bonding pads by conductive links; and iv. said bonding pads are capable of being connected to at least one electrical component placeable upon said surface layer.

Claim 35

A universal interconnect substrate, comprising: a plurality of regularly spaced interconnect cells, each said interconnecting cell comprising: a first intermediate layer comprising a plurality of substantially parallel X-conductors substantially extending the length of said cell; a second intermediate layer comprising a plurality of substantially parallel Y-conductors substantially extending the width of said cell; said X-conductors and said Y-conductors being orthogonal to one another forming non-interrupted cross-over points; and a surface layer configured above said first intermediate layer and said second intermediate layer, said surface layer comprising: i. a plurality of substantially equally spaced bonding pads configured about the outer boundary of each said cell, wherein the spacing between cells is such tat the bonding pad spacing is continuous from cell to cell; ii. a plurality of corner-turning connectors converging inward from said bonding pads, each connector spaced substantially equal distance from adjacent said connector; and wherein iii. said X-conductors and said Y-conductors are capable of being selectively connected to said bonding pads by conductive links; and iv. said bonding pads are capable of being connected to at least one electrical component placeable upon said surface layer.