Chip package board having utility rings

Claim 2

A substrate for an integrated circuit package comprising: an insulative member having opposed first and second sides and having a semiconductor die-attach region on said first side; a pattern of signal members arranged on said first side in spaced relationship to said die-attach region for electrical connection to a semiconductor die within said die-attach region by an array of conductive members; a ground trace extending longitudinally on said first side in a utility region between said signal members and said die-attach region; a power trace extending longitudinally on said first side in said utility region, said power trace being adjacent to said ground trace; at least one around connection means for connecting to electrical ground, said around connection means disposed on said second side; at least one power connection means for connecting to a power source, said power connection means disposed on said second side; at least one ground via extending through said insulative member electrically coupling said around trace to said ground connection means; and at least one power via extending through said insulative member electrically coupling said power trace to said power connection means.

Claim 3

The substrate of claim 1 wherein said utility region surrounds said die-attach region.

Claim 4

The substrate of claim 1 wherein each of said ground trace and said power trace has ring-like configurations.

Claim 5

The substrate of claim 1 wherein said signal members are radially extending signal traces having outer trace ends and inner trace ends, said utility region being adjacent to said inner trace ends.

Claim 6

The substrate of claim 1 wherein said signal members are signal traces extending from inner trace ends to an array of vias that penetrate said insulative member, said second side of said insulative member having a ball grid array of contacts corresponding to said array of vias.

Claim 7

The substrate of claim 1 further comprising conductive vias through said insulative member from said signal members to said second side of said insulative members.

Claim 8

The substrate of claim 3 further comprising a segmented ring-like power trace within said utility region on said first side.

Claim 9

The substrate of claim 7 wherein said ground trace, said power trace and said segmented ring-like power traces are concentrically arranged about said die-connection region.

Claim 10

A chip package comprising: a circuit board having opposed first and second surfaces, said first surface having an inner die-attach region and an outer signal trace region, said first surface further having a utility region surrounding said die-attach region to space said signal trace region from said die-attach region, said circuit board having an array of vias extending from said signal trace region to said second surface of said circuit board; an integrated circuit die attached within said die-attach region of said first surface, said die having four edges and having a plurality of input/output pads; a ground trace within said utility region at each of said four edges of said die, said ground trace being connected to means for connecting to electrical ground; a first power trace within said utility region at each of said four edges of said die, said first power trace being connected to means for connecting to a fixed voltage source; a plurality of second power traces connected to provide at least two different fixed voltages, said second power traces being within said utility region; and an array of conductors having inner wire/lead ends bonded to said input/output pads of said die and having outer wire/lead ends, said outer wire/lead ends including a first plurality connected to said ground trace and a second plurality connected to said power trace, said outer wire/lead ends further including a third plurality connected to sites within said signal trace region.

Claim 11

A chip package comprising: a circuit board having opposed first and second surfaces, said first surface having an inner die-attach region and an outer signal trace region, said first surface further having a utility region surrounding said die-attach region to space said signal trace region from said die-attach region, said circuit board having an array of vias extending from said signal trace region to said second surface of said circuit board; an integrated circuit die attached within said die-attach region of said first surface, said die having four edges and having a plurality of input/output pads; a ground trace within said utility region at each of said four edges of said die, said ground trace being connected to means for connecting to electrical ground; a first power trace within said utility region at each of said four edges of said die, said first power trace being connected to means for connecting to a fixed voltage source; a plurality of second power traces connected to provide at least two different fixed voltages, said second power traces being within said utility region; and an array of conductors having inner wire/lead ends bonded to said input/output pads of said die and having outer wire/lead ends, said outer wire/lead ends including a first plurality connected to said ground trace and a second plurality connected to said power trace, said outer wire/lead ends further including a third plurality connected to sites within said signal trace region.

Claim 12

The chip package of claim 9 wherein said plurality of second power traces is arranged to form a segmented ring-shaped trace around said die-attach region.

Claim 13

The chip package of claim 9 further comprising said means for connecting said power trace to said fixed voltage source, said means for connecting including power vias extending through said circuit board to traces on said second surface of said circuit board.

Claim 14

The chip package of claim 9 wherein said ground trace and said power trace each have a ring-like configuration.

Claim 15

The chip package of claim 9 wherein said vias extending from said signal trace region to said second surface have solder balls at said second surface to form a ball grid array.

Claim 16

The chip package of claim 13 further comprising an array of conductive signal traces within said signal trace region, said signal traces fanning outwardly with departure from said die-attach region, said signal traces having outer trace ends at said vias and having inner trace ends bonded to said outer wire/lead ends of said leadframe.

Claim 17

A substrate for an integrated circuit package comprising: an insulative member having opposed first and second sides and having a semiconductor die-attach region on said first side; a pattern of signal members arranged on said first side in spaced relationship to said die-attach region for electrical connection to a semiconductor die within said die-attach region by an array of conductive members; a ground trace extending longitudinally on said first side in a utility region between said signal members and said die-attach region; a first power trace extending longitudinally on said first side in said utility region, said first power trace being adjacent to said ground trace; and a plurality of second power traces connected to provide at least two different fixed voltages, said second power traces being within said utility region.

Claim 18

A substrate for an integrated circuit package comprising: an insulative member having opposed first and second sides and having a semiconductor die-attach region on said first side; a pattern of signal members arranged on said first side in spaced relationship to said die-attach region for electrical connection to a semiconductor die within said die-attach region by an array of conductive members; a ground trace extending longitudinally on said first side in a utility region between said signal members and said die-attach region; a first power trace extending longitudinally on said first side in said utility region, said first power trace being adjacent to said ground trace; and a plurality of second power traces connected to provide at least two different fixed voltages, said second power traces being within said utility region.

Claim 19

The substrate of claim 15 wherein said utility region surrounds said die-attach region.

Claim 20

The substrate of claim 15 wherein each of said ground trace and said first power trace has ring-like configurations.

Claim 21

The substrate of claim 15 wherein said signal members are radially extending signal traces having outer trace ends and inner trace ends, said utility region being adjacent to said inner trace ends.

Claim 22

The substrate of claim 15 wherein said signal members are signal traces extending from inner trace ends to an array of vias that penetrate said insulative member, said second side of said insulative member having a ball grid array of contacts corresponding to said array of vias.

Claim 23

The substrate of claim 15 further comprising conductive vias through said insulative member from said signal members to said second side of said insulative members.

Claim 24

The substrate of claim 17 wherein said plurality of second power traces is arranged to form a segmented ring-like power trace within said utility region on said first side.

Claim 25

The substrate of claim 21 wherein said ground trace, said first power trace and said segmented ring-like power trace are concentrically arranged about said die-connection region.