Multichip module

Claim 2

An electrical interconnection medium, comprising: an insulating layer; a pattern of conductive vias in the insulating layer; at least first and second overlying interconnection layers, each of the interconnection layers comprising: a plurality of interdigitated first and second parallel conductive regions, the conductive regions of said second interconnection layer being oriented orthogonally to the conductive regions of the first interconnection layer, the conductive regions of the first and second interconnection layers being electrically interconnected such that at least two distinct electrical planes are provided, the first conductive regions of the first and second interconnection layers forming a power plane, the second conductive regions of the firs and second interconnection layers forming a ground plane, portions of each electrical plane appearing on both interconnection layers; an isolated signal path in at least one interconnection layer, said signal path comprising selected isolated and interconnected portions of the first and second conductive regions which otherwise form said power and ground planes; the first conductive regions of the first and second interconnection layers being electrically interconnected by the conductive vias in the insulating layer at every point at which the first conductive regions overlie one another except along said signal path, the second conductive regions of the first and second interconnection layers being electrically interconnected by the conductive vias in the insulating layer at every point at which the second conductive regions overlie one another except along said signal path; pads in at least one of the interconnection layers for making electrical connections to each electrical plane; and at least one pad in the at least one interconnection layer for making electrical connection to the signal path.

Claim 3

The electrical interconnection medium of claim 1, wherein each pad comprises an area where overlying conductive regions of one electrical plane are interconnected, and interdigitated conductive regions of any other electrical plane are omitted.

Claim 4

The electrical interconnection medium of claim 1, further comprising a substrate on which the first layer is formed.

Claim 5

The electrical interconnection medium of claim 3, wherein the substrate comprises an insulating surface on which said first interconnection layer is formed.

Claim 6

The electrical interconnection medium of claim 3, wherein the substrate comprises silicon.

Claim 7

The interconnection medium of claim 1, wherein the medium is a multichip module.

Claim 8

The electrical interconnection medium of claim 1, wherein the insulating layer is a dielectric layer on opposite surfaces of which are positioned the first and second interconnection layers.

Claim 9

The electrical interconnection medium of claim 1, comprising a plurality of signal paths.

Claim 10

A multichip module comprising: an insulating layer with two surfaces; a pattern of conductive vias in the insulating layer; a first interconnecting layer formed on one surface of the insulating layer, the first interconnecting layer comprising a plurality of parallel isolated signal conductive regions and interdigitated first and second conductive regions, the isolated signal conductive regions comprising selected isolated portions of the first and second conductive regions; a second interconnecting layer formed on the other surface of the insulating layer so as to substantially overlie the first interconnecting layer, the second interconnecting layer comprising a further plurality of parallel isolated signal conductive regions and interdigitated first and second conductive regions that are oriented orthogonally to the conductive regions of the first interconnecting layer, said isolated conductive regions in said second interconnecting layer comprising selected isolated portions of the first and second conductive regions in the second interconnecting layer, the conductive regions of said first and second interconnecting layers being interconnected to form at least two distinct electrical planes with portions of each electrical plane appearing on both interconnecting layers, the first conductive regions of the first and second interconnecting layers being electrically interconnected by means of the conductive vias in the insulating layer at every point at which the first conductive regions overlie one another except along said isolated signal conductive regions in the first and second interconnecting layers, the second conductive regions of the first and second interconnecting layers being electrically interconnected by means of the conductive vias in the insulating layer at every point at which the second conductive regions overlie one another except along said isolated conductive regions in said first and second interconnecting layers, the first conductive regions of the first and second interconnecting layers forming a power plane, the second conductive regions of the first and second interconnecting layers forming a ground plane, the isolated signal conductive regions in the first and second interconnecting layers being electrically interconnected by the conductive vias in the insulating layer at every point at which the isolated signal conductive regions overlie one another thereby forming at least one signal path; pads in at least one of the interconnecting layers for making connections to each electrical plane; and pads in at least one interconnecting layer for making connections to the at least one signal path.

Claim 11

A multichip module comprising: an insulating layer with two surfaces; a pattern of conductive vias in the insulating layer; a first interconnecting layer formed on one surface of the insulating layer, the first interconnecting layer comprising a plurality of parallel isolated signal conductive regions and interdigitated first and second conductive regions, the isolated signal conductive regions comprising selected isolated portions of the first and second conductive regions; a second interconnecting layer formed on the other surface of the insulating layer so as to substantially overlie the first interconnecting layer, the second interconnecting layer comprising a further plurality of parallel isolated signal conductive regions and interdigitated first and second conductive regions that are oriented orthogonally to the conductive regions of the first interconnecting layer, said isolated conductive regions in said second interconnecting layer comprising selected isolated portions of the first and second conductive regions in the second interconnecting layer, the conductive regions of said first and second interconnecting layers being interconnected to form at least two distinct electrical planes with portions of each electrical plane appearing on both interconnecting layers, the first conductive regions of the first and second interconnecting layers being electrically interconnected by means of the conductive vias in the insulating layer at every point at which the first conductive regions overlie one another except along said isolated signal conductive regions in the first and second interconnecting layers, the second conductive regions of the first and second interconnecting layers being electrically interconnected by means of the conductive vias in the insulating layer at every point at which the second conductive regions overlie one another except along said isolated conductive regions in said first and second interconnecting layers, the first conductive regions of the first and second interconnecting layers forming a power plane, the second conductive regions of the first and second interconnecting layers forming a ground plane, the isolated signal conductive regions in the first and second interconnecting layers being electrically interconnected by the conductive vias in the insulating layer at every point at which the isolated signal conductive regions overlie one another thereby forming at least one signal path; pads in at least one of the interconnecting layers for making connections to each electrical plane; and pads in at least one interconnecting layer for making connections to the at least one signal path.

Claim 12

The multichip module of claim 9, wherein the insulating layer is a dielectric layer.

Claim 13

The multichip module of claim 9, wherein each pad comprises an area on said at least one interconnecting layer at which conductive regions of a given electrical plane are interconnected and conductive regions of another electrical plane are omitted.

Claim 14

The multichip module of claim 9 comprising a plurality of signal paths.

Claim 15

A multichip module comprising: a substrate having an insulating top surface; first and second overlying interconnecting layers carried on the substrate and separated by an insulating layer, each interconnecting layer comprising parallel isolated signal conductive regions and interdigitated first and second conductive regions, the isolated signal conductive regions comprising selected isolated portions of the first and second conductive regions, the conductive regions of the second interconnecting layer being oriented orthogonally to the conductive regions of the first interconnecting layer, the first and second conductive regions of the first and second interconnecting layers being interconnected to form at least two electrical planes, the first conductive regions of the first and second interconnecting layers being electrically interconnected by conductive vias in the insulating layer at every point at which the first conductive regions overlie one another except along said isolated signal conductive regions, the second conductive regions of the first and second interconnecting layers being electrically interconnected by conductive vias in the insulating layer at every point at which the first conductive regions overlie one another except along said isolated signal conductive regions, the first conductive regions of the first and second interconnecting layers forming a power plane, the second conductive regions of the first and second interconnecting layers forming a ground plane, the isolated signal conductive regions of the first and second interconnecting layers being interconnected by conductive vias in the insulating layer to form at least one signal path; pads for connecting the power, ground and isolated signal conductive regions to electrical components; and a plurality of electrical components connected to said pads.

Claim 16

A multichip module comprising: a substrate having an insulating top surface; first and second overlying interconnecting layers carried on the substrate and separated by an insulating layer, each interconnecting layer comprising parallel isolated signal conductive regions and interdigitated first and second conductive regions, the isolated signal conductive regions comprising selected isolated portions of the first and second conductive regions, the conductive regions of the second interconnecting layer being oriented orthogonally to the conductive regions of the first interconnecting layer, the first and second conductive regions of the first and second interconnecting layers being interconnected to form at least two electrical planes, the first conductive regions of the first and second interconnecting layers being electrically interconnected by conductive vias in the insulating layer at every point at which the first conductive regions overlie one another except along said isolated signal conductive regions, the second conductive regions of the first and second interconnecting layers being electrically interconnected by conductive vias in the insulating layer at every point at which the first conductive regions overlie one another except along said isolated signal conductive regions, the first conductive regions of the first and second interconnecting layers forming a power plane, the second conductive regions of the first and second interconnecting layers forming a ground plane, the isolated signal conductive regions of the first and second interconnecting layers being interconnected by conductive vias in the insulating layer to form at least one signal path; pads for connecting the power, ground and isolated signal conductive regions to electrical components; and a plurality of electrical components connected to said pads.

Claim 17

The multichip module of claim 13, comprising an additional dielectric insulating layer above the second interconnecting layer, the additional insulating layer comprising openings through which electrical connections can be made to said pads.

Claim 18

The multichip module of claim 13, wherein the substrate comprises silicon.

Claim 19

The multichip module of claim 13, wherein the substrate is fabricated with a material selected from the group consisting of silicon, ceramic, glass and aluminum.

Claim 20

The multichip module of claim 14, wherein the insulating layer comprises a polymer.

Claim 21

The multichip module of claim 13 comprising a plurality of signal paths.

Claim 24

An electrical interconnection medium, comprising: a thin dielectric layer; a pattern of conductive vias in the dielectric layer; first and second overlying interconnection layers on opposite sides of the dielectric layer, each of the interconnection layers comprising: a plurality of parallel interdigitated first and second parallel conductive regions, the conductive regions of said second interconnection layer being oriented orthogonally to the conductive regions of the first interconnection layer, the conductive regions of the first and second interconnection layers being electrically interconnected such that at least two distinct electrical planes are provided, the first conductive regions of the first and second interconnection layers forming a power plane, the second conductive regions of the first and second interconnection layers forming a ground plane, portions of each electrical plane appearing on both interconnection layers; isolated signal conductive regions on the first and second interconnecting layers, the isolated signal conductive regions being electrically interconnected by the conductive vias in the insulating layer at every point at which the isolated signal conductive regions overlie one another thereby to form at least one signal path; and the first conductive regions of the first and second interconnection layers being electrically interconnected by conductive vias in said insulating layer at every point at which the first conductive regions overly one another except along said isolated signal conductive regions, the second conductive regions of the first and second interconnection layers being electrically interconnected by the conductive vias in said insulating layer at every point at which the second conductive regions overly one another except along said isolated signal conductive regions.

Claim 25

An electrical interconnection medium, comprising: a thin dielectric layer; a pattern of conductive vias in the dielectric layer; first and second overlying interconnection layers on opposite sides of the dielectric layer, each of the interconnection layers comprising: a plurality of parallel interdigitated first and second parallel conductive regions, the conductive regions of said second interconnection layer being oriented orthogonally to the conductive regions of the first interconnection layer, the conductive regions of the first and second interconnection layers being electrically interconnected such that at least two distinct electrical planes are provided, the first conductive regions of the first and second interconnection layers forming a power plane, the second conductive regions of the first and second interconnection layers forming a ground plane, portions of each electrical plane appearing on both interconnection layers; isolated signal conductive regions on the first and second interconnecting layers, the isolated signal conductive regions being electrically interconnected by the conductive vias in the insulating layer at every point at which the isolated signal conductive regions overlie one another thereby to form at least one signal path; and the first conductive regions of the first and second interconnection layers being electrically interconnected by conductive vias in said insulating layer at every point at which the first conductive regions overly one another except along said isolated signal conductive regions, the second conductive regions of the first and second interconnection layers being electrically interconnected by the conductive vias in said insulating layer at every point at which the second conductive regions overly one another except along said isolated signal conductive regions.