Interconnect structure for integrated circuits

Claim 1

An interconnection structure for semiconductor integrated circuits comprising, a substrate having a plurality of electrical terminal members therein, an electrically conductive metal block disposed over the substrate with a component mounting surface, the metal block containing an electrically conductive wire interconnection pattern, insulated from the metal block, extending from the plurality of electrical terminal members associated with the substrate to the component mounting surface of the block, and a plurality of semiconductor integrated circuits joined to the wire interconnection pattern at the mounting surface.

Claim 6

A method of interconnecting finished integrated circuits with a coaxial transmission line network comprising, (a) building a network of bare electrically conductive wires over a nonconductive substrate in a three dimensional structure extending from chip contact locations to wire terminal members projecting through said substrate at signal interface locations spaced apart from the chip contact locations, (b) coating the built network of bare wires over said substrate with a selected dielectric material to form a plurality of coaxial transmission lines each having an impedance dependent on the ratio of a diameter of the dielectric material to a diameter of the conductive wires, and (c) encapsulating the dielectrically coated bare wires with metal.

Claim 7

A method of interconnecting finished integrated circuits with a coaxial transmission line network comprising, (a) building a network of bare electrically conductive wires over a nonconductive substrate in a three dimensional structure extending from chip contact locations to wire terminal members projecting through said substrate at signal interface locations spaced apart from the chip contact locations, (b) coating the built network of bare wires over said substrate with a selected dielectric material to form a plurality of coaxial transmission lines each having an impedance dependent on the ratio of a diameter of the dielectric material to a diameter of the conductive wires, and (c) encapsulating the dielectrically coated bare wires with metal.

Claim 14

A method for interconnecting finished semiconductor integrated circuits comprising, providing a substrate having a planar upper surface and a plurality of electrical terminal members therein, patterning a first planar layer over the planar substrate surface, the pattern comprising resist regions and electrically conductive metal regions, the metal regions communicating with the electrical terminal members and being x,y sections of a three dimensional wire interconnection pattern, patterning further planar layers, each atop a lower patterned planar layer, the pattern in each layer comprising resist and electrically conductive metal regions and being x,y sections of a three dimensional wire interconnection pattern, the further planar layers defining a z direction for the interconnection pattern wherein x,y and z are orthogonal coordinate directions, the uppermost layer having metal regions in locations corresponding to contact locations of finished semiconductor integrated circuits, removing the resist from all layers, leaving an exposed electrically conductive metal interconnection pattern, coating the metal interconnection pattern, with a coaxial sheath of dielectric material, the coating having a thickness sufficient to prevent electrical shorting between the interconnection pattern and subsequent metal plating, applying metal plating to the dielectric material in a volume forming a support block encapsulating the dielectric coated metal interconnection pattern, and joining finished semiconductor integrated circuits to exposed metal regions in the upper surface of the uppermost layer.

Claim 15

A method for interconnecting finished semiconductor integrated circuits comprising, providing a substrate having a planar upper surface and a plurality of electrical terminal members therein, patterning a first planar layer over the planar substrate surface, the pattern comprising resist regions and electrically conductive metal regions, the metal regions communicating with the electrical terminal members and being x,y sections of a three dimensional wire interconnection pattern, patterning further planar layers, each atop a lower patterned planar layer, the pattern in each layer comprising resist and electrically conductive metal regions and being x,y sections of a three dimensional wire interconnection pattern, the further planar layers defining a z direction for the interconnection pattern wherein x,y and z are orthogonal coordinate directions, the uppermost layer having metal regions in locations corresponding to contact locations of finished semiconductor integrated circuits, removing the resist from all layers, leaving an exposed electrically conductive metal interconnection pattern, coating the metal interconnection pattern, with a coaxial sheath of dielectric material, the coating having a thickness sufficient to prevent electrical shorting between the interconnection pattern and subsequent metal plating, applying metal plating to the dielectric material in a volume forming a support block encapsulating the dielectric coated metal interconnection pattern, and joining finished semiconductor integrated circuits to exposed metal regions in the upper surface of the uppermost layer.

Claim 19

A method of interconnecting finished integrated circuits comprising, building a network of bare electrically conductive wires in a three dimensional structure extending from chip contact locations to signal interface locations spaced apart from the chip contact locations, coating the bare wires with a dielectric material to form a plurality of coaxial transmission lines each having an impedance dependent on the ratio of a diameter of the dielectric material to a diameter of the respective conductive wire, and encapsulating the dielectrically coated bare wires with metal, thereby completing a transmission line network and forming said metal to establish one or more thermally conductive fins.

Claim 20

A method of interconnecting finished integrated circuits comprising, building a network of bare electrically conductive wires in a three dimensional structure extending from chip contact locations to signal interface locations spaced apart from the chip contact locations, coating the bare wires with a dielectric material to form a plurality of coaxial transmission lines each having an impedance dependent on the ratio of a diameter of the dielectric material to a diameter of the respective conductive wire, and encapsulating the dielectrically coated bare wires with metal, thereby completing a transmission line network and forming said metal to establish one or more thermally conductive fins.