Patent US6445030B1 successfully refreshed from Google Patents.
US6445030B1
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Flash memory erase speed by fluorine implant or fluorination
Assignee: Cypress Semiconductor Corp
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Filing: 2001-01-30
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Granted: 2002-09-03
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Expires: 2021-01-30
Abstract
Abstract One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a silicon substrate; a tunnel oxide layer over the silicon substrate, the tunnel oxide layer comprising fluorine atoms; a charge trapping layer over the tunnel oxide layer; an electrode or poly layer over the charge trapping layer; and source and drain regions within the silicon substrate. Another aspect of the present invention relates to a method of making a non-volatile semiconductor memory cell having improved erase speed, involving the steps of providing a silicon substrate; forming a tunnel oxide layer comprising fluorine atoms over the silicon substrate; and forming non-volatile memory cells over the tunnel oxide layer.
Inventors
- 👤 Yider Wu
- 👤 Jean Y. Yang
- 👤 Hidehiko Shiraiwa
- 👤 Che-Hoo Ng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:32
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01346; H10D30/00; H10D30/60; H10D30/69; H10D64/031; H10D64/037; H10D64/60; H10D64/66; H10D64/68; H10D64/681
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
82 words
A non-volatile semiconductor memory device, comprising: a silicon substrate; and SONOS type non-volatile memory cells having improved erase speed on the substrate, each SONOS type memory cell comprising: a tunnel oxide layer having a thickness from about 40 Å to about 250 Å comprising from about 1×10 13 to about 1×10 15 fluorine atoms/cm 2 ; a charge trapping dielectric layer over the tunnel oxide layer; an electrode over the charge trapping layer; and source and drain regions within the silicon substrate.
Claim 2
Dependent Claim
82 words
A non-volatile semiconductor memory device, comprising: a silicon substrate; and SONOS type non-volatile memory cells having improved erase speed on the substrate, each SONOS type memory cell comprising: a tunnel oxide layer having a thickness from about 40 Å to about 250 Å comprising from about 1×10 13 to about 1×10 15 fluorine atoms/cm 2 ; a charge trapping dielectric layer over the tunnel oxide layer; an electrode over the charge trapping layer; and source and drain regions within the silicon substrate.
Claim 3
Dependent Claim
28 words
The non-volatile semiconductor memory device according to claim 1 , wherein the SONOS type non-volatile memory cells have an initial erase time of less than about 500 milliseconds.
Claim 4
Dependent Claim
31 words
The non-volatile semiconductor memory device according to claim 1 , wherein the SONOS type non-volatile memory cells have an erase time of less than about 500 milliseconds after 10,000 program-erase cycles.
Claim 5
Dependent Claim
72 words
The non-volatile semiconductor memory device according to claim 1 , wherein the charge trapping dielectric layer comprises at least one of an ONO trilayer dielectric, an oxide/nitride bilayer dielectric, a nitride/oxide bilayer dielectric, an oxide/tantalum oxide bilayer dielectric, an oxide/tantalum oxide/oxide trilayer dielectric, an oxide/strontium titanate bilayer dielectric, an oxide/barium strontium titanate bilayer dielectric, an oxide/strontium titanate/oxide trilayer dielectric, an oxide/strontium titanate/barium strontium titanate trilayer dielectric, and an oxide/hafnium oxide/oxide trilayer dielectric.
Claim 6
Dependent Claim
35 words
The non-volatile semiconductor memory device according to claim 1 , wherein the charge trapping dielectric layer comprises an ONO dielectric comprising at least one of a nitrided oxide layer and a silicon-rich silicon nitride layer.
Claim 7
Dependent Claim
27 words
The non-volatile semiconductor memory device according to claim 1 , wherein the electrode comprises one of polysilicon, doped polysilicon, doped amorphous silicon, and; a refractory metal silicide.
Claim 8
Dependent Claim
83 words
A SONOS type non-volatile semiconductor memory device comprising at least one SONOS type non-volatile semiconductor memory cell, comprising: a tunnel oxide layer over a silicon substrate, the tunnel oxide layer having a thickness from about 40 Å to about 250 Å comprising from about 1×10 13 to about 1×10 15 fluorine atoms/cm 2 ; an ONO charge trapping dielectric layer over the tunnel oxide layer; an electrode over the ONO charge trapping dielectric layer; and source and drain regions within the silicon substrate.
Claim 9
Dependent Claim
83 words
A SONOS type non-volatile semiconductor memory device comprising at least one SONOS type non-volatile semiconductor memory cell, comprising: a tunnel oxide layer over a silicon substrate, the tunnel oxide layer having a thickness from about 40 Å to about 250 Å comprising from about 1×10 13 to about 1×10 15 fluorine atoms/cm 2 ; an ONO charge trapping dielectric layer over the tunnel oxide layer; an electrode over the ONO charge trapping dielectric layer; and source and drain regions within the silicon substrate.
Claim 10
Dependent Claim
30 words
The SONOS type non-volatile semiconductor memory device according to claim 7 , wherein the SONOS type non-volatile memory cells have an initial erase time of less than about 100 milliseconds.
Claim 11
Dependent Claim
33 words
The SONOS type non-volatile semiconductor memory device according to claim 7 , wherein the SONOS type non-volatile memory cells have an erase time of less than about 100 milliseconds after 10,000 program-erase cycles.
Claim 12
Dependent Claim
33 words
The SONOS type non-volatile semiconductor memory device according to claim 7 , wherein the SONOS type non-volatile memory cells have an erase time of less than about 500 milliseconds after 100,000 program-erase cycles.
Claim 13
Dependent Claim
37 words
The SONOS type non-volatile semiconductor memory device according to claim 7 , wherein the charge trapping dielectric layer comprises an ONO dielectric comprising at least one of a nitrided oxide layer and a silicon-rich silicon nitride layer.
Claim 14
Dependent Claim
29 words
The SONOS type non-volatile semiconductor memory device according to claim 7 , wherein the electrode comprises one of polysilicon, doped polysilicon, doped amorphous silicon, and a refractory metal silicide.
Claim 15
Independent Claim
91 words
A method of making a SONOS type non-volatile semiconductor memory cell having improved erase speed, comprising: providing a silicon substrate; forming a tunnel oxide layer having a thickness from about 40 Å to about 250 Å comprising from about 1×10 13 to about 1×10 15 fluorine atoms/cm 2 over the silicon substrate; forming a charge trapping dielectric over the tunnel oxide layer; forming an electrode over the charge trapping dielectric; forming source and drain regions; and forming SONOS type non-volatile memory cells having improved erase speed over the tunnel oxide layer.
Claim 16
Independent Claim
91 words
A method of making a SONOS type non-volatile semiconductor memory cell having improved erase speed, comprising: providing a silicon substrate; forming a tunnel oxide layer having a thickness from about 40 Å to about 250 Å comprising from about 1×10 13 to about 1×10 15 fluorine atoms/cm 2 over the silicon substrate; forming a charge trapping dielectric over the tunnel oxide layer; forming an electrode over the charge trapping dielectric; forming source and drain regions; and forming SONOS type non-volatile memory cells having improved erase speed over the tunnel oxide layer.
Claim 17
Dependent Claim
32 words
The method according to claim 13 , wherein the tunnel oxide layer is formed by implanting fluorine into the silicon substrate, and growing an oxide layer over the fluorine implanted silicon substrate.
Claim 18
Dependent Claim
26 words
The method according to claim 14 , wherein forming the tunnel oxide layer further comprises heating the oxide layer positioned over the fluorine implanted silicon substrate.
Claim 19
Dependent Claim
30 words
The method according to claim 13 , wherein the tunnel oxide layer is formed by forming an oxide layer over the silicon substrate, and implanting fluorine into the oxide layer.
Claim 20
Dependent Claim
30 words
The method according to claim 13 , wherein the tunnel oxide layer is formed by growing an oxide layer over the silicon substrate in an atmosphere comprising a fluorine compound.
Claim 21
Independent Claim
87 words
A method of increasing erase speed in a SONOS type non-volatile memory cell, comprising: forming a tunnel oxide layer having a thickness from about 40 Å to about 250 Å comprising from about 1×10 13 to about 1×10 15 fluorine atoms/cm 2 over a silicon substrate; forming an ONO charge trapping dielectric over the tunnel oxide layer; forming an electrode over the ONO charge trapping dielectric; forming source and drain regions; and forming SONOS type non-volatile memory cells having increased erase speed over the tunnel oxide layer.
Claim 22
Independent Claim
87 words
A method of increasing erase speed in a SONOS type non-volatile memory cell, comprising: forming a tunnel oxide layer having a thickness from about 40 Å to about 250 Å comprising from about 1×10 13 to about 1×10 15 fluorine atoms/cm 2 over a silicon substrate; forming an ONO charge trapping dielectric over the tunnel oxide layer; forming an electrode over the ONO charge trapping dielectric; forming source and drain regions; and forming SONOS type non-volatile memory cells having increased erase speed over the tunnel oxide layer.
Claim 23
Dependent Claim
68 words
The method according to claim 18 , wherein the tunnel oxide layer is formed by implanting fluorine into the silicon substrate at a dosage from about 1×10 13 to about 1×10 15 atoms/cm 2 at an energy level from about 20 keV to about 80 keV, and growing an oxide layer over the fluorine implanted silicon substrate at a temperature from about 600° C. to about 1,200° C.
Claim 24
Dependent Claim
55 words
The method according to claim 18 , wherein the tunnel oxide layer is formed by forming an oxide layer over the silicon substrate, and implanting fluorine into the oxide layer at a dosage from about 1×10 13 to about 1×10 15 atoms/cm 2 at an energy level from about 20 keV to about 80 keV.
Claim 25
Dependent Claim
41 words
The method according to claim 18 , wherein the tunnel oxide layer is formed by growing an oxide layer over the silicon substrate in an atmosphere comprising a fluorine compound at a temperature from about 600° C. to about 1,200° C.
Claim 26
Dependent Claim
68 words
The method according to claim 13 , wherein the charge trapping dielectric comprises at least one of an ONO trilayer dielectric, an oxide/nitride bilayer dielectric, a nitride/oxide bilayer dielectric, an oxide/tantalum oxide bilayer dielectric, an oxide/tantalum oxide/oxide trilayer dielectric, an oxide/strontium titanate bilayer dielectric, an oxide/barium strontium titanate bilayer dielectric, an oxide/strontium titanate/oxide trilayer dielectric, an oxide/strontium titanate/barium strontium titanate trilayer dielectric, and an oxide/hafnium oxide/oxide trilayer dielectric.
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