Split-Control gate electrically erasable programmable read only memory (EEPROM) cell

Claim 2

A floating gate memory device comprising: a floating gate EEPROM cell formed on a substrate and having a current electrode; a flash memory cell formed on the substrate and having a current electrode; and a charge pump coupled to both the current electrode of the flash memory cell and the current electrode of the floating gate EEPROM cell, the charge pump selectively supplying charge to both the flash memory cell and the floating gate EEPROM cell to enable programming and erasing of both the flash memory cell and the floating gate EEPROM cell wherein a voltage applied to both a source electrode and a drain electrode of the floating gate EEPROM cell does not exceed 5.0 volts for both the programming and erasing of the EEPROM cell.

Claim 3

The floating gate memory device of claim 1 wherein the charge pump supplies a drain voltage of X to the flash memory cell and a drain voltage of Y to the floating gate EEPROM cell wherein X>Y.

Claim 4

The floating gate memory device of claim 1 wherein a voltage applied to both a source and drain current electrode of the floating gate EEPROM cell does not exceed 4.0 volts in absolute value for both the programming and erasing of the EEPROM cell.

Claim 5

The floating gate memory device of claim 1 wherein the EEPROM cell has two control gates wherein a voltage applied to either control gate never exceeds 11.0 volts in absolute value.

Claim 6

A floating gate transistor structure comprising: a substrate comprising silicon; a tunnel oxide less than 100 Angstroms in thickness formed over the substrate; a U-shaped floating gate which is U-shaped when viewed from a top perspective view, the U-shaped floating gate overlying the tunnel oxide wherein the U-shaped floating gate comprises silicon; an inter-level dielectric layer overlying the U-shaped floating gate wherein the inter-level dielectric layer contains a nitride layer and an oxide layer; a first control gate overlying the inter-level dielectric layer and being capacitively coupled to a first portion of the U-shaped floating gate; a second control gate overlying the inter-level dielectric layer, being laterally separated from the first control gate whereby no portion of the second control gate directly overlies a portion of the first control gate, and being capacitively coupled to a second portion of the U-shaped floating gate wherein the first portion is different from the second portion.

Claim 7

A floating gate transistor structure comprising: a substrate comprising silicon; a tunnel oxide less than 100 Angstroms in thickness formed over the substrate; a U-shaped floating gate which is U-shaped when viewed from a top perspective view, the U-shaped floating gate overlying the tunnel oxide wherein the U-shaped floating gate comprises silicon; an inter-level dielectric layer overlying the U-shaped floating gate wherein the inter-level dielectric layer contains a nitride layer and an oxide layer; a first control gate overlying the inter-level dielectric layer and being capacitively coupled to a first portion of the U-shaped floating gate; a second control gate overlying the inter-level dielectric layer, being laterally separated from the first control gate whereby no portion of the second control gate directly overlies a portion of the first control gate, and being capacitively coupled to a second portion of the U-shaped floating gate wherein the first portion is different from the second portion.

Claim 8

The floating gate transistor of claim 5 wherein a select transistor is coupled to the floating gate transistor wherein the select transistor is adapted to selectively control access to the floating gate transistor.

Claim 9

A floating gate memory device comprising: a floating gate EEPROM cell formed on a substrate and having a current electrode, the floating gate EEPROM cell comprising: a drain electrode coupled to a bit line; a source electrode coupled to a source conductor; a channel region located between the source electrode and the drain electrode; a floating gate electrode adjacent the channel region; a first control electrode overlying and adjacent the floating gate electrode, the first control electrode being coupled to a horizontal select control signal; and a second control electrode overlying and adjacent the floating gate electrode, the second control electrode being coupled to a vertical select control signal, whereby the floating gate transistor is either programmed or erased only when both the first and second control electrodes are enabled; a flash memory cell formed on the substrate and having a current electrode; and a charge pump coupled to both the current electrode of the flash memory cell and the current electrode of the floating gate EEPROM cell, the charge pump selectively supplying charge to both the flash memory cell and the floating gate EEPROM cell to enable programming and erasing of both the flash memory cell and the floating gate EEPROM cell wherein a voltage applied to the current electrode of the floating gate EEPROM cell does not exceed 5.0 volts.

Claim 10

A floating gate memory device comprising: a floating gate EEPROM cell formed on a substrate and having a current electrode, the floating gate EEPROM cell comprising: a drain electrode coupled to a bit line; a source electrode coupled to a source conductor; a channel region located between the source electrode and the drain electrode; a floating gate electrode adjacent the channel region; a first control electrode overlying and adjacent the floating gate electrode, the first control electrode being coupled to a horizontal select control signal; and a second control electrode overlying and adjacent the floating gate electrode, the second control electrode being coupled to a vertical select control signal, whereby the floating gate transistor is either programmed or erased only when both the first and second control electrodes are enabled; a flash memory cell formed on the substrate and having a current electrode; and a charge pump coupled to both the current electrode of the flash memory cell and the current electrode of the floating gate EEPROM cell, the charge pump selectively supplying charge to both the flash memory cell and the floating gate EEPROM cell to enable programming and erasing of both the flash memory cell and the floating gate EEPROM cell wherein a voltage applied to the current electrode of the floating gate EEPROM cell does not exceed 5.0 volts.

Claim 11

The floating gate memory device of claim 7 wherein the flash memory cell and the EEPROM cell are both coupled to a central processing unit (CPU) where all of the CPU, flash memory cell, and the EEPROM cell are located on a contiguous silicon substrate.