US6434620B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
TCP/IP offload network interface device
Assignee: Alacritech Inc
•
Filing: 1999-08-27
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Granted: 2002-08-13
•
Expires: 2019-08-27
Abstract
Abstract An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors devoted to transmit, receive and utility processing, providing full duplex communication for four Fast Ethernet nodes.
Inventors
- 👤 Laurence B. Boucher
- 👤 Stephen E. J. Blightman
- 👤 Peter K. Craft
- 👤 David A. Higgen
- 👤 Clive M. Philbrick
- 👤 Daryl D. Starr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:36
CPC Classifications
H; H04; H04L; H04L47/00; H04L47/10; H04L47/19; H04L47/193; G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022; G06F13/42; G06F13/4204; G06F13/4221; H04L45/00; H04L45/66; H04L47/36; H04L47/50; H04L47/62; H04L47/622; H04L47/6225; H04L49/00; H04L49/90; H04L49/901; H04L49/9021; H04L49/9042; H04L49/9047; H04L49/9052; H04L49/9063; H04L49/9068; H04L49/9073; H04L49/9084; H04L49/9089; H04L49/9094; H04L61/00; H04L61/09; H04L61/10; H04L67/00; H04L67/01; H04L67/10; H04L67/34; H04L67/50; H04L67/60; H04L67/62; H04L67/63; H04L69/00; H04L69/12; H04L69/16; H04L69/161; H04L69/163; H04L69/166; H04L69/22; H04L69/162; H04L69/30; H04L69/32
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
127 words
A system, comprising: a processor that performs slow-path network protocol processing, the slow-path network protocol processing being performed substantially in software; and network protocol accelerator circuitry, the network protocol accelerator circuitry receiving a first network communication, the first network communication including a TCP header, the network protocol accelerator circuitry performing fast-path network processing on the first network communication such that the processor performs substantially no TCP protocol processing on the first network communication, the network protocol accelerator circuitry receiving a second network communication, the second network communication including a TCP header, the second network communication being associated with a connection, wherein the processor assumes control of the connection from the network protocol accelerator circuitry, the processor then performing slow-path network protocol processing on the second network communication.
Claim 2
Independent Claim
127 words
A system, comprising: a processor that performs slow-path network protocol processing, the slow-path network protocol processing being performed substantially in software; and network protocol accelerator circuitry, the network protocol accelerator circuitry receiving a first network communication, the first network communication including a TCP header, the network protocol accelerator circuitry performing fast-path network processing on the first network communication such that the processor performs substantially no TCP protocol processing on the first network communication, the network protocol accelerator circuitry receiving a second network communication, the second network communication including a TCP header, the second network communication being associated with a connection, wherein the processor assumes control of the connection from the network protocol accelerator circuitry, the processor then performing slow-path network protocol processing on the second network communication.
Claim 3
Dependent Claim
49 words
The system of claim 1 , wherein the connection is identified by a TCP source port in the second network communication, a TCP destination port in the second network communication, an IP source address in the second network communication, and an IP destination address in the second network communication.
Claim 4
Dependent Claim
34 words
The system of claim 1 , wherein the second network communication is initially fast-path processed by the network protocol accelerator circuitry, and wherein the second network communication is subsequently slow-path processed by the processor.
Claim 5
Dependent Claim
54 words
The system of claim 1 , wherein the first network communication includes a data payload, the network protocol accelerator circuitry receiving the first network communication, determining a final destination, and then placing the data payload into the final destination without the processor performing a substantial amount of fast-path processing on the first network communication.
Claim 6
Dependent Claim
185 words
A protocol accelerator integrated circuit that operates in conjunction with a processor, the processor executing a network protocol stack, the protocol accelerator integrated circuit receiving a first network communication from a network at substantially the same time that it outputs a second network communication to the network, the first network communication including a TCP header and an IP header, the second network communication including a TCP header and an IP header, the protocol accelerator integrated circuit comprising a pipeline of processors, the pipeline of processors including a receive processor and a transmit processor, the receive processor performing protocol processing on the first network communication such that the network protocol stack performs substantially no TCP protocol processing on the first network communication and such that the network protocol stack performs substantially no IP protocol processing on the first network communication, the transmit processor performing protocol processing on the second network communication such that the network protocol stack performs substantially no TCP protocol processing on the second network communication and such that the network protocol stack performs substantially no IP protocol processing on the second network communication.
Claim 7
Dependent Claim
185 words
A protocol accelerator integrated circuit that operates in conjunction with a processor, the processor executing a network protocol stack, the protocol accelerator integrated circuit receiving a first network communication from a network at substantially the same time that it outputs a second network communication to the network, the first network communication including a TCP header and an IP header, the second network communication including a TCP header and an IP header, the protocol accelerator integrated circuit comprising a pipeline of processors, the pipeline of processors including a receive processor and a transmit processor, the receive processor performing protocol processing on the first network communication such that the network protocol stack performs substantially no TCP protocol processing on the first network communication and such that the network protocol stack performs substantially no IP protocol processing on the first network communication, the transmit processor performing protocol processing on the second network communication such that the network protocol stack performs substantially no TCP protocol processing on the second network communication and such that the network protocol stack performs substantially no IP protocol processing on the second network communication.
Claim 8
Dependent Claim
38 words
The protocol accelerator integrated circuit of claim 5 , wherein the protocol accelerator integrated circuit is disposed on a card, and wherein the processor is part of a host computer, the card being coupled to the host computer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-12 | 2006-02-11 | 2006-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-12 | 2010-02-11 | 2010-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-12 | 2014-02-11 | 2014-08-13 | $7700.00 | Window Closed / Lapsed |