Direct memory access unit for transferring data between processor memories in multiprocessing systems

Claim 1

A multi-processing system comprising: a) host processor having a respective host data memory; b) a second processor having a respective second data memory; said second processor being required to have data communication with said host processor; c) a bus providing data communication between said host and second data memories, between said host processor and host data memory, and between said second processor and its second data memory; d) a direct memory access (DMA) controller communicating with said bus and said second data memory for directing transfers of varied-length blocks of data, via said bus, between said host and second data memories on behalf of said second processor, said DMA controller operating in response to control information written to said second data memory by said second processor; said control information defining locations in both said host and second data memories between which said block of data is to be transferred, and the direction in which said block of data is to be transferred; said second processor being capable of writing additional control information to said second data memory while said DMA controller is directing transfer of said block of data; said additional control information defining transfer of one or more additional blocks of data between said host and second data memories; said DMA controller being capable of directing said transfers of both said block of data and said one or more additional blocks of data without having to have any direct communication with either of said host and second processors; and further wherein said control information and said additional control information, respectively defining said transfers of said block of data and said one or more additional blocks of data, further comprise: a) plural control blocks stored in said second memory, said control blocks defining storage locations in both said host and second data memories representing sources and destinations of said data block and said one or more additional data blocks that are to be transferred; and b) a circular queue formed in said second data memory, said circular queue having pointer elements therein, one for each of said control blocks, with each of said pointer elements pointing to the location of the respective control block in said second memory; and wherein said second processor includes: c) means for writing information constituting said plural control blocks to said second data memory and for writing information constituting said pointer elements to said circular queue in said second data memory.

Claim 8

A method of performing direct memory access operations in a multi-processing system that comprises a first processor having a first memory, a second processor having a second memory, and a bus that provides communication between said first processor and its first memory, between said second processor and its second memory, between said first and second processors per se, and between said first and second memories, said method comprising the steps of: a) writing a set of control information from said second processor to said second memory, said set of control information defining a single variable length data block transfer to be conducted between said second and first memories via said bus, said set of control information including information defining locations in both said second and first memories between which said single data block transfer is to be conducted; and b) performing a said direct memory access operation independently of both said second and first processors, to transfer a block of data between said locations in said second and first memories, in accordance with said set of control information written to said second memory by said second processor; said method further comprising steps of: c) extending said step of writing said set of control information to include having plural sets of said control information written to said second memory from said second processor, said plural sets of control information respectively defining different data block transfers to be conducted sequentially between said second and first memories, and each set of control information in said plural sets containing information defining locations in both said second and first memories between which a respective block of data is to be transferred via a respective said direct memory access operation; d) writing plural first pointers, into a circular queue in said second memory, defining locations in said second memory at which said plural sets of control information are stored; and e) providing a second pointer defining locations in said second memory containing said circular queue of first pointers; said second pointer providing a reference for locating all of said first pointers; and f) using said second and first pointers, extending said step of performing said direct memory access operation to include sequentially performing plural direct memory access operations, respectively defined by individual ones of said plural sets of control information stored in said second memory, and thereby transferring plural blocks of data between locations in said second and first memories defined by said plural sets of control information, without requiring further involvement of any of said second processors in any of said operations.

Claim 9

A method of performing direct memory access operations in a multi-processing system that comprises a first processor having a first memory, a second processor having a second memory, and a bus that provides communication between said first processor and its first memory, between said second processor and its second memory, between said first and second processors per se, and between said first and second memories, said method comprising the steps of: a) writing a set of control information from said second processor to said second memory, said set of control information defining a single variable length data block transfer to be conducted between said second and first memories via said bus, said set of control information including information defining locations in both said second and first memories between which said single data block transfer is to be conducted; and b) performing a said direct memory access operation independently of both said second and first processors, to transfer a block of data between said locations in said second and first memories, in accordance with said set of control information written to said second memory by said second processor; said method further comprising steps of: c) extending said step of writing said set of control information to include having plural sets of said control information written to said second memory from said second processor, said plural sets of control information respectively defining different data block transfers to be conducted sequentially between said second and first memories, and each set of control information in said plural sets containing information defining locations in both said second and first memories between which a respective block of data is to be transferred via a respective said direct memory access operation; d) writing plural first pointers, into a circular queue in said second memory, defining locations in said second memory at which said plural sets of control information are stored; and e) providing a second pointer defining locations in said second memory containing said circular queue of first pointers; said second pointer providing a reference for locating all of said first pointers; and f) using said second and first pointers, extending said step of performing said direct memory access operation to include sequentially performing plural direct memory access operations, respectively defined by individual ones of said plural sets of control information stored in said second memory, and thereby transferring plural blocks of data between locations in said second and first memories defined by said plural sets of control information, without requiring further involvement of any of said second processors in any of said operations.