US5488724A — Network controller with memory request and acknow…

Claim 1

Independent Claim 193 words

A network controller for a local system coupled to a network, said local system including a plurality of processors and at least first and second memories for storing data arranged in buffers, said first and second memories respectively being on first and second busses and said first and second busses being connected to a third bus, the network controller comprising: network DMA controller means on said third bus for sending thereon one or the other of a first memory request signal and a second memory request signal to said first and second memories in response to signals from one of said plurality of processors; means coupled to said first bus and responsive only to said first memory request signal for sending a first memory acknowledgement signal to the DMA controller; means coupled to said second bus and responsive only to said second memory request signal for sending a second memory acknowledgement signal to the DMA controller; and wherein said network DMA controller means includes means for accessing only the selected one of said first memory and second memory in response, respectively, to said first memory acknowledgement signal or said second memory acknowledgement signal.

Claim 2

Dependent Claim 193 words

A network controller for a local system coupled to a network, said local system including a plurality of processors and at least first and second memories for storing data arranged in buffers, said first and second memories respectively being on first and second busses and said first and second busses being connected to a third bus, the network controller comprising: network DMA controller means on said third bus for sending thereon one or the other of a first memory request signal and a second memory request signal to said first and second memories in response to signals from one of said plurality of processors; means coupled to said first bus and responsive only to said first memory request signal for sending a first memory acknowledgement signal to the DMA controller; means coupled to said second bus and responsive only to said second memory request signal for sending a second memory acknowledgement signal to the DMA controller; and wherein said network DMA controller means includes means for accessing only the selected one of said first memory and second memory in response, respectively, to said first memory acknowledgement signal or said second memory acknowledgement signal.

Claim 3

Dependent Claim 50 words

The controller of claim 1, wherein said first and second memories comprise, respectively, host and node processor memories for storing at least one of receive data arranged in frames of packets received from the network and transmit data arranged with header and data information to be transmitted to the network.

Claim 4

Dependent Claim 39 words

The controller of claim 2, including means for accessing header information of the transmit data from said node processor memory and for accessing data information of the transmit data from said host processor memory for transmission to the network.

Claim 5

Dependent Claim 17 words

The controller of claim 2, wherein said transmit data are stored in buffers of a descriptor ring.

Claim 6

Dependent Claim 28 words

The controller of claim 1, wherein said first and second memories comprise a plurality of buffers arranged into descriptor rings, each memory having at least one descriptor ring.

Claim 7

Dependent Claim 57 words

The controller of claim 5 further comprising means for splitting receive data into header and data information and storing said header information in said at least one of said buffers of descriptor rings in said first memory and said data information in said at least one of said buffers of said descriptor rings in said second memory.

Claim 8

Dependent Claim 53 words

The controller of claim 5 further comprising means for storing each packet of receive data into buffers of the descriptor rings of said first and second memories, each packet of said receive data having a frame control field and buffers for storing each packet being selected in accordance with said frame control field.

Claim 9

Dependent Claim 64 words

The controller of claim 2, wherein said controller operates in one of a normal mode and a discard mode, said controller further comprising: means for storing packets of said receive data during said normal mode when said first and second memories become full; and means for discarding packets of said receive data during said discard mode when said first and second memories become full.

Claim 10

Independent Claim 187 words

A method of controlling data flow between systems on a network and first and second memories of a local system through a network adapter of the local system, said first and second memories storing data arranged in buffers, respectively, being on first and second buses, and said first and second buses being connected to a third bus and a DMA controller being coupled to the third bus, the method of controlling data flow comprising the steps of: sending on said third bus one or the other of a first memory request signal and a second memory request signal to access a selected one of said first and second memories in response to signals from a processor of the local system; in response to only said first memory request signal on the first bus, sending a first memory acknowledgement signal to the DMA controller; in response to only said second memory request signal on the second bus, sending a second memory acknowledgement signal to the DMA controller; and in response to said first and second acknowledgement signals, accessing only the selected one of said first and second memories.

Claim 11

Independent Claim 187 words

A method of controlling data flow between systems on a network and first and second memories of a local system through a network adapter of the local system, said first and second memories storing data arranged in buffers, respectively, being on first and second buses, and said first and second buses being connected to a third bus and a DMA controller being coupled to the third bus, the method of controlling data flow comprising the steps of: sending on said third bus one or the other of a first memory request signal and a second memory request signal to access a selected one of said first and second memories in response to signals from a processor of the local system; in response to only said first memory request signal on the first bus, sending a first memory acknowledgement signal to the DMA controller; in response to only said second memory request signal on the second bus, sending a second memory acknowledgement signal to the DMA controller; and in response to said first and second acknowledgement signals, accessing only the selected one of said first and second memories.

Claim 12

Dependent Claim 60 words

The method of claim 9 further comprising the steps of: storing receive data from said network in the selected one of said first and second memories during a receive mode of the local system; and transferring transmit data stored in the selected one of said first and second memories to said network during a transmit mode of the local system.

Claim 13

Dependent Claim 72 words

The method of claim 9 further comprising the steps of: storing receive data from said network in a temporary buffer during a normal mode of operation of the network adapter when the selected one of said first and second memories becomes full; and discarding incoming receive data from said network during a discard mode of operation of the network adapter when the selected one of said first and second memories becomes full.

Claim 14

Dependent Claim 192 words

A network adapter for coupling a local system to a network comprising: a first memory on a first bus; a second memory on a second bus; a network controller on a third bus, said first and second busses being coupled to said third bus, and said network controller sending one or the other of a first memory request signal and a second memory request signal to said first and second memories in response to signals from a CPU of the local system; means coupled to said first bus and responsive only to said first memory request signal for sending a first memory acknowledgement signal to said network controller, and means coupled to said second bus and responsive only to said second memory request signal for sending a second memory acknowledgement signal to said network controller, wherein said network controller further includes means for accessing only the selected one of said first and second memories in response, respectively, to said first or second acknowledgement signal; and means for transferring receive data from said network to said local system and transmit data from said local system to said network coupled to said network controller.

Claim 15

Dependent Claim 192 words

A network adapter for coupling a local system to a network comprising: a first memory on a first bus; a second memory on a second bus; a network controller on a third bus, said first and second busses being coupled to said third bus, and said network controller sending one or the other of a first memory request signal and a second memory request signal to said first and second memories in response to signals from a CPU of the local system; means coupled to said first bus and responsive only to said first memory request signal for sending a first memory acknowledgement signal to said network controller, and means coupled to said second bus and responsive only to said second memory request signal for sending a second memory acknowledgement signal to said network controller, wherein said network controller further includes means for accessing only the selected one of said first and second memories in response, respectively, to said first or second acknowledgement signal; and means for transferring receive data from said network to said local system and transmit data from said local system to said network coupled to said network controller.

Claim 16

Dependent Claim 108 words

The network adaptor of claim 12, wherein said transferring means comprises: medium access controller means coupled to said network controller for at least one of performing proper network access protocol, receiving and transmitting frames of receive data and transmit data and carrying out any required housekeeping functions; coding means coupled to said medium access controller and said network for converting said receive data and transmit data into proper format for reception of said receive data by the network adaptor and for transmission of said transmit data to said network; and buffer means coupled to said medium access controller and said network controller for temporary storing said receive data.

Claim 17

Dependent Claim 51 words

The network adaptor of claim 12, wherein said first and second memories comprise, respectively, host and node processor memories for storing at least one of receive data arranged in frames of packets received from the network and transmit data arranged with header and data information to be transmitted to the network.

Claim 18

Dependent Claim 42 words

The network adaptor of claim 14 further comprising means for accessing said header information of the transmit data from said node processor memory and for accessing data information of the transmit data from said host processor memory for transmission to the network.

Claim 19

Dependent Claim 18 words

The network adaptor of claim 14, wherein said transmit data are stored in buffers of a descriptor ring.

Claim 20

Dependent Claim 29 words

The network adaptor of claim 12, wherein said first and second memories comprise a plurality of buffers arranged into descriptor rings, each memory having at least one descriptor ring.

Claim 21

Dependent Claim 53 words

The network adaptor of claim 17 further comprising means for splitting receive data into header and data information and storing said header information in said at least one of said descriptor rings of said first memory and said data information in said at least one of said descriptor rings in said second memory.

Claim 22

Dependent Claim 54 words

The network adaptor of claim 17 further comprising means for storing each packet of receive data into buffers of the descriptor rings of said first and second memories, each packet of said receive data having a frame control field and buffers for storing each packet being selected in accordance with said frame control field.

Claim 23

Dependent Claim 67 words

The network adaptor of claim 14, wherein said network controller operates in one of a normal mode and a discard mode, said network controller further comprising: means for storing packets of said receive data during said normal mode when said first and second memories become full; and means for discarding packets of said receive data during said discard mode when said first and second memories become full.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-01-29	1999-07-31	2000-01-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-01-29	2003-07-31	2004-01-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-01-29	2007-07-31	2008-01-30	$7700.00	Window Closed / Lapsed

Network controller with memory request and acknowledgement signals and a network adapter therewith

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