US5093780A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Inter-processor transmission system having data link which automatically and periodically reads and writes the transfer data
Assignee: Fujitsu Ltd
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Filing: 1989-10-18
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Granted: 1992-03-03
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Expires: 2009-10-18
Abstract
Abstract An inter-processor transmission system comprises first and second processors which are coupled via a data link apparatus. The first processor simply writes transfer data into a memory which is coupled thereto with a predetermined period, and the data link apparatus automatically reads the transfer data from the memory and transfers the read transfer data to a memory which is coupled to the second processor in a direct memory access mode.
Inventors
- 👤 Hazime Sunahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:33
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/14; G06F13/20; G06F13/28; G06F15/00; G06F15/16; G06F15/163; G06F15/17
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
188 words
An inter-processor transmission system comprising: a first processor; a first memory; a first bus which couples said first processor and said first memory; a second processor; a second memory; a second bus which couples said second processor and said second memory; and a data link apparatus which is coupled between said first and second buses, said data link apparatus comprising: a transmitter part which is coupled to said first bus; and a receiver part which is coupled to said second bus, said first processor comprising: means for initially setting once first control information in said transmitter part; and means for periodically writing according to a predetermined period transfer data which is to be transmitted into said first memory, said second processor comprising: means for initially setting once second control information in said receiver part, said transmitter part automatically and periodically reading the transfer data from said first memory based on the first control information and transferring the transfer data to said receiver part, said receiver part automatically and periodically writing the transfer data received from said transmitter part into said second memory based on the second control information.
Claim 2
Dependent Claim
188 words
An inter-processor transmission system comprising: a first processor; a first memory; a first bus which couples said first processor and said first memory; a second processor; a second memory; a second bus which couples said second processor and said second memory; and a data link apparatus which is coupled between said first and second buses, said data link apparatus comprising: a transmitter part which is coupled to said first bus; and a receiver part which is coupled to said second bus, said first processor comprising: means for initially setting once first control information in said transmitter part; and means for periodically writing according to a predetermined period transfer data which is to be transmitted into said first memory, said second processor comprising: means for initially setting once second control information in said receiver part, said transmitter part automatically and periodically reading the transfer data from said first memory based on the first control information and transferring the transfer data to said receiver part, said receiver part automatically and periodically writing the transfer data received from said transmitter part into said second memory based on the second control information.
Claim 3
Dependent Claim
66 words
The inter-processor transmission system as claimed in claim 1 wherein said first control information includes a start address of the transfer data which is written in said first memory, a length of the transfer data, and a free-running period that is a constant with which the transmitter part reads the transfer data from said first memory and transfers the read transfer data to said receiver part.
Claim 4
Dependent Claim
31 words
The inter-processor transmission system as claimed in claim 2 wherein said second control information includes a start address where the received transfer data is to be written in said second memory.
Claim 5
Dependent Claim
46 words
The inter-processor transmission system as claimed in claim 3 wherein said transmitter part includes, means for repeating the transfer of the read transfer data to said receiver part for a number of times corresponding to the number of transfer data included in said first control information.
Claim 6
Dependent Claim
22 words
The inter-processor transmission system as claimed in claim 2 wherein said predetermined period is greater than or equal to the free-running period.
Claim 7
Dependent Claim
27 words
The inter-processor transmission system as claimed in claim 1 wherein said free-running period is less than or equal to an anticipated minimum value of said predetermined period.
Claim 8
Dependent Claim
121 words
The inter-processor transmission system as claimed in claim 1 wherein said transmitter part comprises a first data region in which said first control information is set, a first direct memory access apparatus coupled to said first bus, a transmitter coupled to said first direct memory access apparatus and said receiver part, and a timer which is started based on said first control information for triggering said first direct memory access apparatus and said transmitter, said first direct memory access apparatus reading the transfer data from said first memory and transferring the read transfer data to said transmitter in the direct memory access mode, said transmitter transmitting the read transfer data received from said direct memory access apparatus to said receiver part.
Claim 9
Dependent Claim
71 words
The inter-processor transmission system as claimed in claim 7 wherein said receiver part comprises a second data region in which said second control information is set, a receiver for receiving the read transfer data from said transmitter, and a second direct memory access apparatus coupled to said receiver and said second bus for transferring the transfer data received by said receiver to said second memory based on said second control information.
Claim 10
Dependent Claim
42 words
The inter-processor transmission system as claimed in claim 8 wherein said transmitter of said transmitter part transmits a predetermined mark indicating that a first word of the transfer data is being transmitted prior to transferring the first word of the transfer data.
Claim 11
Dependent Claim
58 words
The inter-processor transmission system as claimed in claim 9 wherein said receiver part further comprises a data analyzer coupled to said receiver and said second direct memory access apparatus for detecting whether or not the received transfer data is the predetermined mark and for initially resetting said second direct memory access apparatus when the predetermined mark is detected.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-03 | 1995-09-02 | 1996-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-03 | 1999-09-02 | 2000-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-03 | 2003-09-02 | 2004-03-03 | $7700.00 | Window Closed / Lapsed |