Patent US6430718B1 successfully refreshed from Google Patents.
US6430718B1
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Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom
Assignee: Rambus Inc
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Filing: 1999-08-30
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Granted: 2002-08-06
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Expires: 2019-08-30
Abstract
Abstract Architecture, circuitry, and methods are provided for testing one or more integrated circuits which may be arranged upon a printed circuit board. The integrated circuits include sequential and combinatorial logic used by the integrated circuit during normal functioning thereof. Testing of that logic can occur by sending test vectors in parallel or serial form to input pins of the integrated circuit. The test results can either be read as a serial data stream or as a parallel-delivered data stream. If the test information and results occur in parallel fashion, than automated test equipment can be used which do not require compliance with having a single serial fed test vector input and test result output, normally found in a TAP application. A parallel/serial multiplexer is used to select whether the integrated circuit receives parallel or serial test vectors, and another parallel/serial multiplexer is used to select whether the test results are to be delivered in parallel or serial fashion. A test access port controller is linked to various boundary scan cells, and control signal generators within the controller orchestrate movement of test data or normal functional data into and from the integrated circuit core logic. Parallel fed test vectors can be shifted from the input cells as serial fed test vectors and then back to the input cells, where the test vectors can then be sent to the core logic among numerous conductors in parallel fashion. Likewise, the test results can be converted from a parallel to serial form and fed back to the output cells, whereupon the test results can be sent to the test equipment as parallel-delivered test results.
Inventors
- 👤 Anup K. Nayak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:03
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
70 words
Test architecture, comprising: an integrated circuit having a plurality of input pins adapted to receive a parallel delivered test signal; a singular input pin adapted to receive a serial delivered test signal; and a first multiplexer coupled to directly present to a plurality of scan elements within a core logic of the integrated circuit either the serial delivered test signal or the parallel delivered test signal converted to serial format.
Claim 2
Dependent Claim
70 words
Test architecture, comprising: an integrated circuit having a plurality of input pins adapted to receive a parallel delivered test signal; a singular input pin adapted to receive a serial delivered test signal; and a first multiplexer coupled to directly present to a plurality of scan elements within a core logic of the integrated circuit either the serial delivered test signal or the parallel delivered test signal converted to serial format.
Claim 3
Dependent Claim
28 words
The test architecture as recited in claim 1 , further comprising a plurality of serially linked input boundary scan cells coupled to respective said plurality of input pins.
Claim 4
Dependent Claim
58 words
The test architecture as recited in claim 2 , further comprising: a plurality of output pins; and a second multiplexer coupled to the input boundary scan cells and the scan elements to selectively present either an output from the input boundary scan cells or an output from the scan elements in parallel to the plurality of output pins.
Claim 5
Dependent Claim
94 words
Test architecture, comprising: an integrated circuit having a logic portion and a plurality of input pins adapted to receive a parallel delivered test signal; a plurality of boundary scan cells adapted to convert the parallel delivered test signal into a serial test signal; and a plurality of scan elements adapted to receive the serial test signal, wherein the scan elements comprise a plurality of capture latches configured to deliver the serial test signal to a plurality of update latches before sending the serial test signal in parallel fashion to circuitry within the logic portion.
Claim 6
Dependent Claim
94 words
Test architecture, comprising: an integrated circuit having a logic portion and a plurality of input pins adapted to receive a parallel delivered test signal; a plurality of boundary scan cells adapted to convert the parallel delivered test signal into a serial test signal; and a plurality of scan elements adapted to receive the serial test signal, wherein the scan elements comprise a plurality of capture latches configured to deliver the serial test signal to a plurality of update latches before sending the serial test signal in parallel fashion to circuitry within the logic portion.
Claim 7
Dependent Claim
41 words
The test architecture as recited in claim 4 , wherein an input of one of the plurality of update latches is connected to an output of one of the plurality of capture latches, each of which are clocked at dissimilar times.
Claim 8
Dependent Claim
43 words
The test architecture as recited in claim 4 , wherein the serial test signal is shifted through the plurality of capture latches by using a clocking signal which transitions a number of times proportional to the number of said plurality of capture latches.
Claim 9
Dependent Claim
29 words
The test architecture as recited in claim 4 , wherein the serial test signal is forwarded across a single conductor that is routed between the plurality of capture latches.
Claim 10
Dependent Claim
33 words
The test architecture as recited in claim 7 , wherein the single conductor is routed from the integrated circuit to another integrated circuit, both of which are interconnected upon a printed circuit board.
Claim 11
Dependent Claim
18 words
The test architecture as recited in claim 4 , wherein the logic portion comprises sequential and/or combinatorial logic.
Claim 12
Dependent Claim
49 words
The test architecture as recited in claim 4 , wherein the plurality of boundary scan cells comprises a second plurality of capture latches and update latches, and wherein the plurality of boundary scan cells are interconnected between respective said plurality of input pins and the plurality of scan elements.
Claim 13
Dependent Claim
170 words
A semiconductor substrate, comprising: a plurality of input pins adapted to receive a parallel delivered test signal; a single input pin adapted to receive a serial delivered test signal; a first multiplexer adapted to directly present either the parallel delivered test signal converted to serial format or the serial delivered test signal to a plurality of scan elements within a core logic of an integrated circuit; and a test access port (TAP) controller coupled between the single input pin and the first multiplexer, wherein the TAP controller comprises: a first control signal generator adapted to capture a test signal, wherein the test signal comprises either the parallel delivered test signal converted to serial format or the serial delivered test signal; a first clock signal generator adapted to serially shift the test signal across the plurality of scan elements; and a second control signal generator adapted to dispense, in parallel, portions of the test signal from the plurality of scan elements onto separate conductors coupled to circuitry within the core logic.
Claim 14
Dependent Claim
170 words
A semiconductor substrate, comprising: a plurality of input pins adapted to receive a parallel delivered test signal; a single input pin adapted to receive a serial delivered test signal; a first multiplexer adapted to directly present either the parallel delivered test signal converted to serial format or the serial delivered test signal to a plurality of scan elements within a core logic of an integrated circuit; and a test access port (TAP) controller coupled between the single input pin and the first multiplexer, wherein the TAP controller comprises: a first control signal generator adapted to capture a test signal, wherein the test signal comprises either the parallel delivered test signal converted to serial format or the serial delivered test signal; a first clock signal generator adapted to serially shift the test signal across the plurality of scan elements; and a second control signal generator adapted to dispense, in parallel, portions of the test signal from the plurality of scan elements onto separate conductors coupled to circuitry within the core logic.
Claim 15
Dependent Claim
15 words
The semiconductor substrate as recited in claim 11 , wherein the portions comprise test data.
Claim 16
Dependent Claim
20 words
The semiconductor substrate as recited in claim 11 , wherein the portions comprise at least one bit of test data.
Claim 17
Dependent Claim
49 words
The semiconductor substrate as recited in claim 11 , wherein the first control generator is configured to produce a first control signal, said first clock signal generator is configured to produce a first clock signal, and said second control signal generator is adapted to produce a second control signal.
Claim 18
Dependent Claim
35 words
The semiconductor substrate as recited in claim 14 , wherein the first control signal is produced prior to the first clock signal, and the first clock signal is produced prior to the second control signal.
Claim 19
Dependent Claim
36 words
The semiconductor substrate as recited in claim 11 , wherein each of the plurality of scan elements comprises an input latch coupled to receive output from the first multiplexer and produce output to a second multiplexer.
Claim 20
Independent Claim
55 words
A method for testing an integrated circuit, comprising: applying a test signal to a plurality of input pins of an integrated circuit; shifting the test signal onto a single conductor; and drawing from the single conductor portions of the test signal to be forwarded in parallel to combinatorial and sequential logic within the integrated circuit.
Claim 21
Independent Claim
55 words
A method for testing an integrated circuit, comprising: applying a test signal to a plurality of input pins of an integrated circuit; shifting the test signal onto a single conductor; and drawing from the single conductor portions of the test signal to be forwarded in parallel to combinatorial and sequential logic within the integrated circuit.
Claim 22
Dependent Claim
22 words
The method as recited in claim 17 , wherein said applying comprises coupling a multi-output test signal generator to the input pins.
Claim 23
Dependent Claim
40 words
The method as recited in claim 17 , further comprising selecting the test signal applied to the plurality of input pins rather than another test signal applied to a test access port (TAP) serial input conductor of the integrated circuit.
Claim 24
Dependent Claim
30 words
The method as recited in claim 17 , further comprising capturing the test signal within a plurality of capture latches prior to shifting the test signal upon the single conductor.
Claim 25
Dependent Claim
46 words
The method as recited in claim 17 , further comprising forwarding results of the test signal upon the combinatorial and sequential logic to a plurality of output pins of the integrated circuit or a single test access port (TAP) serial output conductor of the integrated circuit.
Claim 26
Dependent Claim
35 words
The method as recited in claim 17 , wherein said shifting comprises clocking the test signal across a plurality of scan devices by clocking a plurality of capture latches coupled to receive the test signal.
Claim 27
Dependent Claim
20 words
The method as recited in claim 22 , wherein said scan devices comprise either boundary scan cells or scan elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-05 | 2006-02-04 | 2006-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-05 | 2010-02-04 | 2010-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-05 | 2014-02-04 | 2014-08-06 | $7700.00 | Window Closed / Lapsed |