US5805607A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for user-controlled I/O switching during in-circuit programming of CPLDs through the IEEE 1149.1 test access port
Assignee: Lattice Semiconductor Corp
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Filing: 1996-10-22
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Granted: 1998-09-08
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Expires: 2016-10-22
Abstract
Abstract A programmable logic device operable to generate different control signals during a time interval when it is being reconfigured includes a plurality of I/O pins (18a-18f), boundary scan circuitry (14) operatively connected to the I/O pins for loading a new set of data and for driving the new set of data onto the I/O pins, and means for programming (33) the programmable logic device on a row-by-row basis when loaded with program instructions. Control circuitry (31a) is provided to control the programming means to be operated on a self-timed interval for programming each row so that the boundary scan circuitry can be loaded with additional sets of data to generate the different control signals. The control circuitry includes a programming timer register (70) and a programming status register (68).
Inventors
- 👤 Arthur H. Khu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:15
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318516
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
311 words
A programmable logic device operable to generate different control signals during a time interval when it is being reconfigured in order to increase the rate at which data can be changed on I/O Dins, said programmable logic device comprising: a plurality of I/O pins (18a-18f); boundary scan circuit means (14) operatively connected to said I/O pins for loading a new set of data and for driving said new set of data onto said I/O pins; means for programming (33) said programmable logic device on a row-by-row basis when loaded with program instructions; timer means (70) for counting a predetermined amount of programming time and being started in response to the loading of the program instructions into said programming means; said timer means being formed of a programming timer register (70) which either counts down to zero or counts up to a predetermined value when said program instructions are loaded; indicator means (68) being set prior to the loading of said program instructions into said programming means for generating a status signal when said timer means has completed counting said predetermined amount of programming time; said indicator means being formed of a programming status resister (68) which is set before programming of each row; logic circuit means (39a) being responsive to said status signal and said programming time for causing said programming means to halt the programming of a particular row; said boundary scan circuit means capable of being loaded with additional sets of data to generate the different control signals during the time interval between the start of programming of the particular row and before the loading of programming data for the next row; and the loading of said boundary scan circuit means with said additional sets of data being temporarily suspended until the program instructions, programming data and programming time have been loaded and said programming means has been started.
Claim 2
Dependent Claim
311 words
A programmable logic device operable to generate different control signals during a time interval when it is being reconfigured in order to increase the rate at which data can be changed on I/O Dins, said programmable logic device comprising: a plurality of I/O pins (18a-18f); boundary scan circuit means (14) operatively connected to said I/O pins for loading a new set of data and for driving said new set of data onto said I/O pins; means for programming (33) said programmable logic device on a row-by-row basis when loaded with program instructions; timer means (70) for counting a predetermined amount of programming time and being started in response to the loading of the program instructions into said programming means; said timer means being formed of a programming timer register (70) which either counts down to zero or counts up to a predetermined value when said program instructions are loaded; indicator means (68) being set prior to the loading of said program instructions into said programming means for generating a status signal when said timer means has completed counting said predetermined amount of programming time; said indicator means being formed of a programming status resister (68) which is set before programming of each row; logic circuit means (39a) being responsive to said status signal and said programming time for causing said programming means to halt the programming of a particular row; said boundary scan circuit means capable of being loaded with additional sets of data to generate the different control signals during the time interval between the start of programming of the particular row and before the loading of programming data for the next row; and the loading of said boundary scan circuit means with said additional sets of data being temporarily suspended until the program instructions, programming data and programming time have been loaded and said programming means has been started.
Claim 3
Dependent Claim
28 words
A programmable logic device as claimed in claim 1, wherein said timer register is controlled by a user-specified frequency signal for controlling the duration of the programming operation.
Claim 4
Dependent Claim
36 words
A programmable logic device as claimed in claim 1, wherein said timer register is controlled by an external frequency signal which is different from a user-specified frequency signal for controlling the duration of the programming operation.
Claim 5
Dependent Claim
22 words
A programmable logic device as claimed in claim 1, wherein said boundary scan circuit means is comprised of boundary scan registers (14a-14f).
Claim 6
Dependent Claim
23 words
A programmable logic device as claimed in claim 4, wherein said boundary scan registers are formed of a plurality of boundary-scan cells (44-48).
Claim 7
Dependent Claim
20 words
A programmable logic device as claimed in claim 1, wherein said timer means is controlled by another separate external pin.
Claim 8
Independent Claim
207 words
A method of operating a programmable logic device to generate different control signals during a time interval when it is being reconfigured in order to increase the rate at which data can be changed on I/O pins, said method comprising the steps of: loading a new set of data in boundary scan circuitry operatively connected to I/O pins; driving the new set of data onto the I/O pins; programming the programmable logic device on a row-by-row basis when loaded with program instructions; counting for a predetermined amount of programming time which is started after the program instructions are loaded; generating a status signal after counting for the predetermined amount of programming time has been completed; halting the programminga of a particular row in response to the status signal and the programming time; loading the boundary scan circuitry with additional sets of data to generate the different control signals during the time interval between the start of programming of the particular row and before the loading of programming data for the next row; and suspending temporarily the loading of the boundary scan circuitry with the additional sets of data until the program instructions, programming data and programming time have been loaded and the programming step has been started.
Claim 9
Independent Claim
207 words
A method of operating a programmable logic device to generate different control signals during a time interval when it is being reconfigured in order to increase the rate at which data can be changed on I/O pins, said method comprising the steps of: loading a new set of data in boundary scan circuitry operatively connected to I/O pins; driving the new set of data onto the I/O pins; programming the programmable logic device on a row-by-row basis when loaded with program instructions; counting for a predetermined amount of programming time which is started after the program instructions are loaded; generating a status signal after counting for the predetermined amount of programming time has been completed; halting the programminga of a particular row in response to the status signal and the programming time; loading the boundary scan circuitry with additional sets of data to generate the different control signals during the time interval between the start of programming of the particular row and before the loading of programming data for the next row; and suspending temporarily the loading of the boundary scan circuitry with the additional sets of data until the program instructions, programming data and programming time have been loaded and the programming step has been started.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-07 | 2002-03-09 | 2002-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-07 | 2006-03-09 | 2006-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-07 | 2010-03-09 | 2010-09-08 | $7700.00 | Window Closed / Lapsed |