Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks

Claim 2

A programmable logic array integrated circuit device comprising: a plurality of logic regions, each of which has a plurality of input terminals and at least one output terminal, and each of which is programmable to produce at its output terminal an output logic signal which is any of a plurality of logic functions of input logic signals applied to its input terminals, said logic regions being grouped in a plurality of blocks such that each of said blocks includes a respective sub-plurality of adjacent ones of said logic regions, and said blocks being grouped in a plurality of super-blocks such that each of said super-blocks includes a respective sub-plurality of adjacent ones of said blocks; a plurality of inter-super-block circuits configured to convey signals between the super-blocks; a plurality of super-block-feeding circuits associated with each of said super-blocks and disposed adjacent the logic regions of the associated super-block; a first programmable logic connector array associated with each of said pluralities of super-block-feeding circuits and configured to selectively connect said super-block-feeding circuits to the inter-super-block circuits; and a second programmable logic connector array associated with each of said pluralities of super-block-feeding circuits and configured for selective connection of said super-block-feeding circuits to the input terminals of the logic regions in the super-block with which said super-block-feeding circuits are associated, each such connection requiring only a single conductor and a single programmable logic connector.

Claim 3

A programmable logic device comprising: a plurality of repetitions of all elements defined in claim 1 ; and interconnection circuitry configured to convey signals between said repetitions.

Claim 4

The device defined in claim 1 further comprising: a third programmable logic connector array associated with each of said super-blocks and configured to selectively connect the output terminals of the logic regions in said super-block to the inter-super-block circuits.

Claim 5

The device defined in claim 1 wherein the super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns of said super-blocks.

Claim 6

The device defined in claim 2 wherein each of said repetitions is disposed on the device in a respective one of a plurality of rows, and wherein the interconnection circuitry includes conductors that extend transverse to said rows.

Claim 7

The device defined in claim 5 wherein the inter-super-block circuits in each of said repetitions include additional conductors that extend substantially parallel to the rows.

Claim 8

A programmable logic array integrated circuit device comprising: a plurality of logic regions, each of which has a plurality of input terminals and at least one output terminal, and each of which is programmable to produce at its output terminal an output logic signal which is any of a plurality of logic functions of input logic signals applied to its input terminals, said logic regions being grouped in a plurality of blocks such that each of said blocks includes a respective sub-plurality of adjacent ones of said logic regions, and said blocks being grouped in a plurality of super-blocks such that each of said super-blocks includes a respective sub-plurality of adjacent ones of said blocks; a plurality of inter-super-block circuits configured to convey signals between the super-blocks; a plurality of super-block-feeding circuits associated with each of said super-blocks and disposed adjacent the logic regions of the associated super-block; a first programmable logic connector array associated with each of said pluralities of super-block-feeding circuits and configured to selectively connect said super-block-feeding circuits to the inter-super-block circuits; a second programmable logic connector array associated with each of said pluralities of super-block-feeding circuits and configured to selectively connect said super-block-feeding circuits to the input terminals of the logic regions in the super-block with which said super-block-feeding circuits are associated; and a plurality of local feedback circuits associated with each of said super-blocks and configured to locally feed back to input terminals of the logic regions in said super-block the output logic signals of the logic regions in said super-block.

Claim 9

A programmable logic array integrated circuit device comprising: a plurality of logic regions, each of which has a plurality of input terminals and at least one output terminal, and each of which is programmable to produce at its output terminal an output logic signal which is any of a plurality of logic functions of input logic signals applied to its input terminals, said logic regions being grouped in a plurality of blocks such that each of said blocks includes a respective sub-plurality of adjacent ones of said logic regions, and said blocks being grouped in a plurality of super-blocks such that each of said super-blocks includes a respective sub-plurality of adjacent ones of said blocks; a plurality of inter-super-block circuits configured to convey signals between the super-blocks; a plurality of super-block-feeding circuits associated with each of said super-blocks and disposed adjacent the logic regions of the associated super-block; a first programmable logic connector array associated with each of said pluralities of super-block-feeding circuits and configured to selectively connect said super-block-feeding circuits to the inter-super-block circuits; a second programmable logic connector array associated with each of said pluralities of super-block-feeding circuits and configured to selectively connect said super-block-feeding circuits to the input terminals of the logic regions in the super-block with which said super-block-feeding circuits are associated; and a plurality of local feedback circuits associated with each of said super-blocks and configured to locally feed back to input terminals of the logic regions in said super-block the output logic signals of the logic regions in said super-block.

Claim 10

The device defined in claim 7 further comprising: a third programmable logic connector array associated with each of said super-blocks and configured to selectively connect the output terminals of the logic regions in said super-block to the inter-super-block circuits.

Claim 11

The device defined in claim 7 wherein the super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns of said super-blocks.

Claim 12

A programmable logic device comprising: a plurality of repetitions of all elements defined in claim 7 ; and interconnection circuitry configured to convey signals between said repetitions.

Claim 13

The device defined in claim 10 wherein each of said repetitions is disposed on the device in a respective one of a plurality of rows, and wherein the interconnection circuitry includes conductors that extend transverse to said rows.

Claim 14

The device defined in claim 11 wherein the inter-super-block circuits in each of said repetitions include additional conductors that extend substantially parallel to the rows.