Patent US6388284B2 successfully refreshed from Google Patents.
US6388284B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Capacitor structures
Assignee: Mosaid Technologies Inc
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Filing: 2001-01-03
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Granted: 2002-05-14
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Expires: 2021-01-03
Abstract
Abstract Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereover. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.
Inventors
- 👤 Howard E. Rhodes
- 👤 Lyle D. Breiner
- 👤 Philip J. Ireland
- 👤 Trung Tri Doan
- 👤 Gurtej S. Sandhu
- 👤 Sujit Sharan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:49
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; H10D1/01; H10D1/041; H10D1/042; H10D1/62; H10D1/66; H10D1/714; H10D1/716; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
206 words
A capacitor comprising: a substrate having a node location; a field effect transistor gate proximate the node location, the field effect transistor gate having a top and a sidewall proximate the node location which are covered with insulative material; an insulative layer disposed over the substrate and on the insulative material, the insulative layer having an opening over the node location and the insulative material; a first polysilicon material layer having a first conductivity only partially filling the insulative layer opening, the first polysilicon material layer being disposed within the opening in contacting relationship with both the insulative layer and the insulative material covering the gate sidewall, and operably connected with the node location; a second polysilicon material layer over the first polysilicon material layer and received within and only partially filling the opening, the second polysilicon material layer having an outermost surface within the opening which has a generally roughened surface area; a non-polysilicon conductive layer over the second polysilicon material layer's outermost surface received within and only partially filling the opening, the non-polysilicon conductive layer having a second conductivity which is greater than the first conductivity; a capacitor dielectric layer over the conductive material layer; and a capacitor plate over the capacitor dielectric layer.
Claim 2
Dependent Claim
206 words
A capacitor comprising: a substrate having a node location; a field effect transistor gate proximate the node location, the field effect transistor gate having a top and a sidewall proximate the node location which are covered with insulative material; an insulative layer disposed over the substrate and on the insulative material, the insulative layer having an opening over the node location and the insulative material; a first polysilicon material layer having a first conductivity only partially filling the insulative layer opening, the first polysilicon material layer being disposed within the opening in contacting relationship with both the insulative layer and the insulative material covering the gate sidewall, and operably connected with the node location; a second polysilicon material layer over the first polysilicon material layer and received within and only partially filling the opening, the second polysilicon material layer having an outermost surface within the opening which has a generally roughened surface area; a non-polysilicon conductive layer over the second polysilicon material layer's outermost surface received within and only partially filling the opening, the non-polysilicon conductive layer having a second conductivity which is greater than the first conductivity; a capacitor dielectric layer over the conductive material layer; and a capacitor plate over the capacitor dielectric layer.
Claim 3
Dependent Claim
22 words
The capacitor of claim 1 , wherein the capacitor plate comprises a cell plate layer which constitutes a portion of DRAM circuitry.
Claim 4
Dependent Claim
15 words
The capacitor of claim 1 , wherein the second polysilicon material comprises hemispherical grain polysilicon.
Claim 5
Dependent Claim
18 words
The capacitor of claim 1 , wherein the non-polysilicon conductive layer comprises elemental titanium or a titanium alloy.
Claim 6
Dependent Claim
13 words
The capacitor of claim 1 , wherein the non-polysilicon conductive layer comprises TiN.
Claim 7
Dependent Claim
13 words
The capacitor of claim 1 , wherein the non-polysilicon conductive layer comprises platinum.
Claim 8
Dependent Claim
22 words
The capacitor of claim 1 wherein the non-polysilicon layer is at least in partial physical contacting relationship with the capacitor dielectric layer.
Claim 9
Dependent Claim
37 words
The capacitor of claim 1 wherein the node location comprises a diffusion region formed in semiconductor material, and the first polysilicon material layer is formed in physical contact with the diffusion region formed in the semiconductor material.
Claim 10
Dependent Claim
219 words
A capacitor comprising: a substrate having a node location; a field effect transistor gate proximate the node location, the field effect transistor gate having a top and a sidewall proximate the node location which are covered with insulative material; an insulative layer disposed over the substrate and over the insulative material, the insulative layer having an opening over the node location; a first polysilicon material layer having a first conductivity only partially filling the insulative layer opening, the first polysilicon material layer being disposed within the opening and operably connected with the node location; a second polysilicon material layer over the first polysilicon material layer and received within and only partially filling the opening, the second polysilicon material layer having an outermost surface within the opening which has a generally roughened surface area, the second polysilicon material layer having a planar uppermost surface; a non-polysilicon conductive layer over the second polysilicon material layer's outermost surface received within and only partially filling the opening, the non-polysilicon conductive layer having a second conductivity which is greater than the first conductivity, the non-polysilicon conductive layer having a planar uppermost surface which is coplanar with the planar uppermost surface of the second polysilicon material layer; a capacitor dielectric layer over the conductive material layer; and a capacitor plate over the capacitor dielectric layer.
Claim 11
Dependent Claim
219 words
A capacitor comprising: a substrate having a node location; a field effect transistor gate proximate the node location, the field effect transistor gate having a top and a sidewall proximate the node location which are covered with insulative material; an insulative layer disposed over the substrate and over the insulative material, the insulative layer having an opening over the node location; a first polysilicon material layer having a first conductivity only partially filling the insulative layer opening, the first polysilicon material layer being disposed within the opening and operably connected with the node location; a second polysilicon material layer over the first polysilicon material layer and received within and only partially filling the opening, the second polysilicon material layer having an outermost surface within the opening which has a generally roughened surface area, the second polysilicon material layer having a planar uppermost surface; a non-polysilicon conductive layer over the second polysilicon material layer's outermost surface received within and only partially filling the opening, the non-polysilicon conductive layer having a second conductivity which is greater than the first conductivity, the non-polysilicon conductive layer having a planar uppermost surface which is coplanar with the planar uppermost surface of the second polysilicon material layer; a capacitor dielectric layer over the conductive material layer; and a capacitor plate over the capacitor dielectric layer.
Claim 12
Dependent Claim
22 words
The capacitor of claim 9 , wherein the capacitor plate comprises a cell plates layer which constitutes a portion of DRAM circuitry.
Claim 13
Dependent Claim
15 words
The capacitor of claim 9 , wherein the second polysilicon material comprises hemispherical grain polysilicon.
Claim 14
Dependent Claim
18 words
The capacitor of claim 9 , wherein the non-polysilicon conductive layer comprises elemental titanium or a titanium alloy.
Claim 15
Dependent Claim
13 words
The capacitor of claim 9 , wherein the non-polysilicon conductive layer comprises TiN.
Claim 16
Dependent Claim
13 words
The capacitor of claim 9 , wherein the non-polysilicon conductive layer comprises platinum.
Claim 17
Dependent Claim
37 words
The capacitor of claim 9 , wherein the capacitor dielectric layer is received over and contacting both the planar uppermost surface of the non-polysilicon conductive layer and the planar uppermost surface of the second polysilicon material layer.
Claim 18
Dependent Claim
254 words
A capacitor comprising: a substrate having a node location; a field effect transistor gate proximate the node location, the field effect transistor gate having a top and a sidewall proximate the node location which are covered with insulative material; an insulative layer disposed over the substrate and over the insulative material, the insulative layer having an opening over the node location; a first polysilicon material layer having a first conductivity only partially filling the insulative layer opening, the first polysilicon material layer being disposed within the opening and operably connected with the node location, the first polysilicon material layer having a planar uppermost surface; a second polysilicon material layer over the first polysilicon material layer and received within and only partially filling the opening, the second polysilicon material layer having an outermost surface within the opening which has a generally roughened surface area, the second polysilicon material layer having a planar uppermost surface which is coplanar with the planar uppermost surface of the first polysilicon material layer; a non-polysilicon conductive layer over the second polysilicon material layer's outermost surface received within and only partially filling the opening, the non-polysilicon conductive layer having a second conductivity which is greater than the first conductivity, the non-polysilicon conductive layer having a planar uppermost surface which is coplanar with the planar uppermost surface of the second polysilicon material layer and the planar uppermost surface of the first polysilicon material layer; a capacitor dielectric layer over the conductive material layer; and a capacitor plate over the capacitor dielectric layer.
Claim 19
Dependent Claim
254 words
A capacitor comprising: a substrate having a node location; a field effect transistor gate proximate the node location, the field effect transistor gate having a top and a sidewall proximate the node location which are covered with insulative material; an insulative layer disposed over the substrate and over the insulative material, the insulative layer having an opening over the node location; a first polysilicon material layer having a first conductivity only partially filling the insulative layer opening, the first polysilicon material layer being disposed within the opening and operably connected with the node location, the first polysilicon material layer having a planar uppermost surface; a second polysilicon material layer over the first polysilicon material layer and received within and only partially filling the opening, the second polysilicon material layer having an outermost surface within the opening which has a generally roughened surface area, the second polysilicon material layer having a planar uppermost surface which is coplanar with the planar uppermost surface of the first polysilicon material layer; a non-polysilicon conductive layer over the second polysilicon material layer's outermost surface received within and only partially filling the opening, the non-polysilicon conductive layer having a second conductivity which is greater than the first conductivity, the non-polysilicon conductive layer having a planar uppermost surface which is coplanar with the planar uppermost surface of the second polysilicon material layer and the planar uppermost surface of the first polysilicon material layer; a capacitor dielectric layer over the conductive material layer; and a capacitor plate over the capacitor dielectric layer.
Claim 20
Dependent Claim
22 words
The capacitor of claim 16 , wherein the capacitor plate comprises a cell plate layer which constitutes a portion of DRAM circuitry.
Claim 21
Dependent Claim
15 words
The capacitor of claim 16 , wherein the second polysilicon material comprises hemispherical grain polysilicon.
Claim 22
Dependent Claim
18 words
The capacitor of claim 16 , wherein the non-polysilicon conductive layer comprises elemental titanium or a titanium alloy.
Claim 23
Dependent Claim
13 words
The capacitor of claim 16 , wherein the non-polysilicon conductive layer comprises TiN.
Claim 24
Dependent Claim
13 words
The capacitor of claim 16 , wherein the non-polysilicon conductive layer comprises platinum.
Claim 25
Dependent Claim
48 words
The capacitor of claim 16 , wherein the capacitor dielectric layer is received over and contacting each of the planar uppermost surface of the non-polysilicon conductive layer, the planar uppermost surface of the second polysilicon material layer, and the planar uppermost surface of the first polysilicon material layer.
Claim 26
Dependent Claim
215 words
A capacitor comprising: a substrate having a node location; a field effect transistor gate proximate the node location, the field effect transistor gate having a top and a sidewall proximate the node location which are covered with insulative material; an insulative layer disposed over the substrate and over the insulative material, the insulative layer having an opening over the node location, the insulative layer having a planar uppermost surface; a first polysilicon material layer having a first conductivity only partially filling the insulative layer opening, the first polysilicon material layer being disposed within the opening and operably connected with the node location; a second polysilicon material layer over the first polysilicon material layer and received within and only partially filling the opening, the second polysilicon material layer having an outermost surface within the opening which has a generally roughened surface area; a non-polysilicon conductive layer over the second polysilicon material layer's outermost surface received within and only partially filling the opening, the non-polysilicon conductive layer having a second conductivity which is greater than the first conductivity, the non-polysilicon conductive layer having a planar uppermost surface which is coplanar with the planar uppermost surface of the insulative layer; a capacitor dielectric layer over the conductive material layer; and a capacitor plate over the capacitor dielectric layer.
Claim 27
Dependent Claim
215 words
A capacitor comprising: a substrate having a node location; a field effect transistor gate proximate the node location, the field effect transistor gate having a top and a sidewall proximate the node location which are covered with insulative material; an insulative layer disposed over the substrate and over the insulative material, the insulative layer having an opening over the node location, the insulative layer having a planar uppermost surface; a first polysilicon material layer having a first conductivity only partially filling the insulative layer opening, the first polysilicon material layer being disposed within the opening and operably connected with the node location; a second polysilicon material layer over the first polysilicon material layer and received within and only partially filling the opening, the second polysilicon material layer having an outermost surface within the opening which has a generally roughened surface area; a non-polysilicon conductive layer over the second polysilicon material layer's outermost surface received within and only partially filling the opening, the non-polysilicon conductive layer having a second conductivity which is greater than the first conductivity, the non-polysilicon conductive layer having a planar uppermost surface which is coplanar with the planar uppermost surface of the insulative layer; a capacitor dielectric layer over the conductive material layer; and a capacitor plate over the capacitor dielectric layer.
Claim 28
Dependent Claim
22 words
The capacitor of claim 23 , wherein the capacitor plate comprises a cell plate layer which constitutes a portion of DRAM circuitry.
Claim 29
Dependent Claim
15 words
The capacitor of claim 23 , wherein the second polysilicon material comprises hemispherical grain polysilicon.
Claim 30
Dependent Claim
18 words
The capacitor of claim 23 , wherein the non-polysilicon conductive layer comprises elemental titanium or a titanium alloy.
Claim 31
Dependent Claim
13 words
The capacitor of claim 23 , wherein the non-polysilicon conductive layer comprises TiN.
Claim 32
Dependent Claim
13 words
The capacitor of claim 23 , wherein the non-polysilicon conductive layer comprises platinum.
Claim 33
Dependent Claim
35 words
The capacitor of claim 23 , wherein the capacitor dielectric layer is received over and contacting both the planar uppermost surface of the non-polysilicon conductive layer and the planar uppermost surface of the insulating layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-05-13 | 2005-11-12 | 2006-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-05-13 | 2009-11-12 | 2010-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-05-13 | 2013-11-12 | 2014-05-14 | $7700.00 | Window Closed / Lapsed |