Patent US6353249B1 successfully refreshed from Google Patents.
US6353249B1
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MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
Assignee: Elpis Technologies Inc
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Filing: 2001-05-25
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Granted: 2002-03-05
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Expires: 2021-05-25
Abstract
Abstract Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/μm or below) and a channel length (sub-lithographic, e.g., 0.1 μm or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.
Inventors
- 👤 Diane Catherine Boyd
- 👤 Hussein Ibrahim Hanafi
- 👤 Meikei Ieong
- 👤 Wesley Charles Natzle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:49
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D30/01; H10D30/021; H10D30/0212; H10D30/0223; H10D30/0225; H10D30/0227; H10D30/601; H10D64/01304; H10D64/01324; H10D64/01342; H10D64/017; H10D64/021; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/683; H10D64/691
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
75 words
A MOSFET device comprising at least one gate region formed on a semiconductor substrate, said gate region comprising a gate conductor, a gate insulator and spacers, said gate insulator is a high-k metal oxide having a dielectric constant of greater than 7.0, said gate region further comprising a sub-lithographic channel formed beneath said gate insulator, wherein said channel length is determined by forming a portion of said gate insulator on a tapered pad oxide layer.
Claim 2
Dependent Claim
75 words
A MOSFET device comprising at least one gate region formed on a semiconductor substrate, said gate region comprising a gate conductor, a gate insulator and spacers, said gate insulator is a high-k metal oxide having a dielectric constant of greater than 7.0, said gate region further comprising a sub-lithographic channel formed beneath said gate insulator, wherein said channel length is determined by forming a portion of said gate insulator on a tapered pad oxide layer.
Claim 3
Dependent Claim
21 words
The MOSFET device of claim 1 wherein said semiconductor substrate is comprised of Si, Ge, SiGe, GaP, InAs, InP or Si/SiGe.
Claim 4
Dependent Claim
16 words
The MOSFET device of claim 1 wherein said gate conductor comprises polysilicon, W, Ta or TiN.
Claim 5
Dependent Claim
31 words
The MOSFET device of claim 1 wherein said high-k metal oxide comprises Al 2 O 3 , TiO 2 , ZrO 2 , barium titanate, strontium titanate or barium strontium titanate.
Claim 6
Dependent Claim
20 words
The MOSFET device of claim 1 wherein said semiconductor substrate contains dielectric filled isolation trenches adjacent to said gate region.
Claim 7
Dependent Claim
16 words
The MOSFET device of claim 1 where said spacers are comprised of an oxide or nitride.
Claim 8
Dependent Claim
24 words
The MOSFET device of claim 1 wherein source and dram regions are formed in said semiconductor substrate beneath a portion of said gate region.
Claim 9
Dependent Claim
16 words
The MOSFET device of claim 7 further comprising source/drain extensions adjoining said source and drain regions.
Claim 10
Dependent Claim
15 words
The MOSFET device of claim 1 wherein a silicide is formed atop said gate region.
Claim 11
Dependent Claim
17 words
The MOSFET device of claim 7 wherein silicide regions are formed over said source and drain regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-03-04 | 2005-09-03 | 2006-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-03-04 | 2009-09-03 | 2010-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-03-04 | 2013-09-03 | 2014-03-05 | $7700.00 | Window Closed / Lapsed |