← Back to Patent Explorer
US6008095A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for formation of isolation trenches with high-K gate dielectrics

Assignee: Advanced Micro Devices Inc
•
Filing: 1998-08-07
•
Granted: 1999-12-28
•
Expires: 2018-08-07
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A process for formation of isolation trenches with high-k gate dielectrics. In an example embodiment, the process comprises depositing a high permittivity layer on the substrate. An isolation trench extending from the high permittivity layer into the substrate is etched at a selected location on the substrate. The high permittivity layer is then etched to a selected thickness, and gate electrodes are formed adjacent the trench on the high permittivity layer of the selected thickness. In another embodiment, the isolation trench is formed with an oxide liner using an NO anneal, and the high-K gate dielectric layer is optionally reduced in thickness.

Inventors

  • 👤 Mark I. Gardner
  • 👤 H. Jim Fulford
  • 👤 Charles E May

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 20:16
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0151; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17

Claims Analysis

Total Claims: 32
Claim 1
Independent Claim 80 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate; wherein the high permittivity layer material has a dielectric constant of at least 20; forming an isolation trench extending from the high permittivity layer into the substrate at a selected location on the substrate; etching away the high permittivity layer to a selected thickness; and forming gate electrodes adjacent the trench on the high permittivity layer of the selected thickness.
Claim 2
Dependent Claim 80 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate; wherein the high permittivity layer material has a dielectric constant of at least 20; forming an isolation trench extending from the high permittivity layer into the substrate at a selected location on the substrate; etching away the high permittivity layer to a selected thickness; and forming gate electrodes adjacent the trench on the high permittivity layer of the selected thickness.
Claim 3
Dependent Claim 60 words
The process of claim 1, further comprising: implanting a first concentration of a first dopant species into the substrate after formation of the gate electrodes; forming spacers on the high permittivity layer beside the gate electrodes; removing the high permittivity layer between spacers of adjacent gate electrodes; and implanting a second concentration of a second dopant species into the substrate.
Claim 4
Dependent Claim 14 words
The process of claim 2, wherein etching comprises plasma etching the high permittivity layer.
Claim 5
Dependent Claim 22 words
The process of claim 3, further comprising depositing a polysilicon layer over the high permittivity layer after etching the high permittivity layer.
Claim 6
Dependent Claim 32 words
The process of claim 1, wherein the high permittivity layer is comprised of material selected from the group of barium strontium titanate, tantalum oxide, lead zinc niobate, and lead scandium tantalum oxide.
Claim 7
Dependent Claim 13 words
The process of claim 1, wherein the gate electrodes comprise highly doped polysilicon.
Claim 8
Dependent Claim 12 words
The process of claim 1, wherein the gate electrodes comprise a metal.
Claim 9
Dependent Claim 12 words
The process of claim 1, wherein the gate electrodes comprise titanium nitride.
Claim 10
Dependent Claim 12 words
The process of claim 1, wherein the gate electrodes comprise titanium tungsten.
Claim 11
Dependent Claim 116 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate; wherein the high permittivity layer material has a dielectric constant of at least 20; forming a trench through the high permittivity layer and in the substrate at a selected location on the substrate; depositing oxide in the trench; forming gate electrodes adjacent the trench on the high permittivity layer; implanting a first concentration of a first dopant species into the substrate; forming spacers on the high permittivity layer beside the gate electrodes; removing the high permittivity layer between spacers of adjacent gate electrodes; and implanting a second concentration of a second dopant species into the substrate.
Claim 12
Dependent Claim 116 words
A process for forming a semiconductor structure on a silicon substrate, comprising: depositing a high permittivity layer on the substrate; wherein the high permittivity layer material has a dielectric constant of at least 20; forming a trench through the high permittivity layer and in the substrate at a selected location on the substrate; depositing oxide in the trench; forming gate electrodes adjacent the trench on the high permittivity layer; implanting a first concentration of a first dopant species into the substrate; forming spacers on the high permittivity layer beside the gate electrodes; removing the high permittivity layer between spacers of adjacent gate electrodes; and implanting a second concentration of a second dopant species into the substrate.
Claim 13
Dependent Claim 33 words
The process of claim 10, further comprising: planarizing the oxide in the trench with the high permittivity layer; and reducing the high permittivity layer to a selected thickness before forming the gate electrodes.
Claim 14
Dependent Claim 14 words
The process of claim 11, wherein reducing comprises plasma etching the high permittivity layer.
Claim 15
Dependent Claim 22 words
The process of claim 12, further comprising depositing a polysilicon layer over the high permittivity layer after etching the high permittivity layer.
Claim 16
Dependent Claim 25 words
The process of claim 11, further comprising oxidizing walls of the trench in the presence of NO gas prior to depositing oxide in the trench.
Claim 17
Dependent Claim 25 words
The process of claim 10, further comprising oxidizing walls of the trench in the presence of NO gas prior to depositing oxide in the trench.
Claim 18
Dependent Claim 16 words
The process of claim 10, wherein the high permittivity layer is comprised of barium strontium titanate.
Claim 19
Dependent Claim 15 words
The process of claim 10, wherein the high permittivity layer is comprised of tantalum oxide.
Claim 20
Dependent Claim 16 words
The process of claim 10, wherein the high permittivity layer is comprised of lead zinc niobate.
Claim 21
Dependent Claim 17 words
The process of claim 10, wherein the high permittivity layer is comprised of lead scandium tantalum oxide.
Claim 22
Dependent Claim 13 words
The process of claim 10, wherein the gate electrodes comprise highly doped polysilicon.
Claim 23
Dependent Claim 12 words
The process of claim 10, wherein the gate electrodes comprise a metal.
Claim 24
Dependent Claim 12 words
The process of claim 10, wherein the gate electrodes comprise titanium nitride.
Claim 25
Dependent Claim 12 words
The process of claim 10, wherein the gate electrodes comprise titanium tungsten.
Claim 26
Dependent Claim 20 words
The process of claim 10, wherein the first dopant species is selected from the group of boron, phosphorus, or arsenic.
Claim 27
Dependent Claim 24 words
The process of claim 24, wherein the first concentration of the first dopant species is in the range of approximately 8e14-3e15 ions/cm 2 .
Claim 28
Dependent Claim 26 words
The process of claim 25, wherein the first dopant species is implanted with an energy level in the range of approximately 0.5 KeV to 5 KeV.
Claim 29
Dependent Claim 20 words
The process of claim 24, wherein the second dopant species is selected from the group of boron, phosphorus, or arsenic.
Claim 30
Dependent Claim 26 words
The process of claim 27, wherein the second dopant species is implanted with an energy level in the range of approximately 0.2 KeV to 5 KeV.
Claim 31
Dependent Claim 23 words
The process of claim 28, wherein the second dopant species is implanted with a dose rate of approximately 2E15-6 E15 ions/cm 2 .
Claim 32
Dependent Claim 18 words
The process of claim 10, wherein the high permittivity layer has a dielectric constant of at least 20.

References Cited (Backward Citations)

US5420060A Cited
US5292673A Cited
US5834348A Cited
US5679599A Cited
US5741722A Cited
US5777370A Cited
US5786256A Cited
US5763310A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-12-27 2003-06-28 2003-12-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-12-27 2007-06-28 2007-12-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-12-27 2011-06-28 2011-12-28 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag