US5763310A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit employing simultaneously formed isolation and transistor trenches
Assignee: GlobalFoundries Inc
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Filing: 1996-10-08
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Granted: 1998-06-09
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Expires: 2016-10-08
Abstract
Abstract A semiconductor fabrication process in which a transistor trench and an isolation trench are simultaneously formed in a semiconductor substrate. The transistor trench is laterally displaced from the isolation trench. Thereafter the isolation trench is filled with an isolation material and a gate dielectric is formed on the floor of the transistor trench. Next, a conductive gate is formed on the gate dielectric and a source/drain impurity distribution is introduced into a source region and a drain region of the semiconductor substrate. The drain region and the source region are laterally disposed on either side of the transistor trench. In a presently preferred embodiment, the semiconductor substrate comprises a substantially single crystal p+ silicon bulk and a p- epitaxial layer formed upon the p+ silicon bulk. Preferably, the process of forming a transistor trench and the isolation trench includes depositing a photoresist layer on an upper surface of the semiconductor substrate, patterning the photoresist layer to expose an upper surface of an isolation trench region and an upper surface of a transistor trench region, anisotropically etching the isolation trench and the transistor trench region with a chlorinated plasma and stripping the photoresist layer. The process of filling the isolation trench with an isolation material preferably comprises depositing an isolation dielectric on the topography defined by the upper surface of the semiconductor substrate and the isolation trench and removing the isolation dielectric from regions exterior to the isolation trench.
Inventors
- 👤 Mark I. Gardner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:51
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/025; H10D64/027; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
115 words
A semiconductor fabrication process, comprising: providing a semiconductor substrate; forming a transistor trench and, simultaneously, an isolation trench in said semiconductor substrate, wherein said transistor trench is laterally displaced from said isolation trench; filling said isolation trench with an isolation material; forming a gate dielectric on a floor of said transistor trench subsequent to the step of filling said isolation trench with an isolation material; forming a conductive gate on said gate dielectric; and introducing a source/drain impurity distribution into a source region and a drain region of said semiconductor substrate subsequent to the step of forming said conductive gate, wherein said transistor trench is laterally disposed between said source region and said drain region.
Claim 2
Dependent Claim
115 words
A semiconductor fabrication process, comprising: providing a semiconductor substrate; forming a transistor trench and, simultaneously, an isolation trench in said semiconductor substrate, wherein said transistor trench is laterally displaced from said isolation trench; filling said isolation trench with an isolation material; forming a gate dielectric on a floor of said transistor trench subsequent to the step of filling said isolation trench with an isolation material; forming a conductive gate on said gate dielectric; and introducing a source/drain impurity distribution into a source region and a drain region of said semiconductor substrate subsequent to the step of forming said conductive gate, wherein said transistor trench is laterally disposed between said source region and said drain region.
Claim 3
Dependent Claim
27 words
The process of claim 1, wherein said semiconductor substrate comprises a substantially single crystal p+ silicon bulk and a p- epitaxial layer upon said p+ silicon bulk.
Claim 4
Dependent Claim
73 words
The process of claim 1 wherein the step of forming said transistor trench and said isolation trench comprises: depositing a photoresist layer upon an upper surface of said semiconductor substrate; patterning said photoresist layer to expose an upper surface of an isolation trench region and an upper surface of a transistor trench region; anisotropically etching said isolation trench region and said transistor trench region with a chlorinated plasma; and stripping said photoresist layer.
Claim 5
Dependent Claim
51 words
The process of claim 1 wherein the step of filling said isolation trench with an isolation material comprises: depositing an isolation dielectric upon a topography cooperatively defined by said upper surface of said semiconductor substrate and said isolation trench; and removing said isolation dielectric from regions exterior to said isolation trench.
Claim 6
Dependent Claim
27 words
The process of claim 4 wherein said isolation dielectric comprises chemical vapor deposited oxide formed from a source selected from the group consisting of TEOS or silane.
Claim 7
Dependent Claim
12 words
The process of claim 4 wherein said removing comprises chemical mechanical polishing.
Claim 8
Dependent Claim
42 words
The process of claim 1 wherein the step of forming said gate dielectric comprises thermally oxidizing said trench floor such that said gate dielectric comprises a thermal oxide and wherein a thickness of said thermal oxide is approximately 20 to 200 angstroms.
Claim 9
Dependent Claim
36 words
The process of claim 1 wherein the step of form said conductive gate comprises: chemical vapor depositing a polysilicon layer on said gate dielectric; and removing portions of said polysilicon layer exterior to said transistor trench.
Claim 10
Dependent Claim
12 words
The process of claim 8 wherein said removing comprises chemical mechanical polishing.
Claim 11
Dependent Claim
28 words
The process of claim 1 wherein the step of introducing said source/drain impurity distribution comprises ion implanting impurities selected from the group consisting of boron, phosphorous, and arsenic.
Claim 12
Dependent Claim
42 words
The process of claim 10 wherein an implant energy of said ion implanting is such that a peak concentration of said source/drain impurity distribution is located a depth below said upper surface approximately one half of a depth of said transistor trench.
Claim 13
Dependent Claim
26 words
The process of claim 11 wherein said source/drain impurity distribution extends to a depth below said upper surface approximately equal to a depth of said transistor.
Claim 14
Dependent Claim
32 words
The process of claim 10 wherein said ion implanting simultaneously introduces said impurities into said conductive gate such that a sheet resistivity of said conductive gate is less than approximately 500 Ω/square.
Claim 15
Dependent Claim
99 words
The process of claim 1 further comprising, prior to the forming of said gate dielectric: filling said transistor trench with a spacer material; and forming a spacer structure within said transistor trench by removing a portion of said spacer material displaced over a channel region of said semiconductor substrate, wherein said channel region extends laterally approximately from a first sidewall of said transistor trench to an intermediate position between said first sidewall and a second sidewall of said transistor trench such that a lateral dimension of said channel region is less than a lateral dimension of said transistor trench.
Claim 16
Dependent Claim
32 words
The process of claim 14 wherein the step of filling said transistor trench comprises chemical vapor depositing an oxide formed from a source selected from the group consisting of TEOS and silane.
Claim 17
Dependent Claim
78 words
The process of claim 14 further comprising, subsequent to said introducing: removing an upper portion of said spacer structure to form an implant displacement structure; and introducing a source side impurity distribution into a source side impurity region of said semiconductor substrate, wherein said source side impurity region extends approximately from said second sidewall of said transistor trench to said channel region such that said source side impurity distribution electrically connects said source region to said channel region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-08 | 2001-12-08 | 2002-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-08 | 2005-12-08 | 2006-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-08 | 2009-12-08 | 2010-06-09 | $7700.00 | Window Closed / Lapsed |