US5093273A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device
Assignee: Toshiba Corp
•
Filing: 1990-07-03
•
Granted: 1992-03-03
•
Expires: 2010-07-03
Abstract
Abstract A semiconductor device comprising three recessed portions formed at a very small pitch on the surface of a semiconductor substrate, remaining regions formed between these recessed portions as impurity diffused regions serving as the source and the drain, respectively, and a conductive region as a gate electrode formed through an insulating film within the central recessed portion, and a method of manufacturing such a semiconductor device are disclosed. With this device, its gate length can be made shorter than that in the prior art and the junction leakage is reduced, resulting in miniaturization and an improvement in the characteristics.
Inventors
- 👤 Katsuya Okumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:31
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; G; G03; G03F; G03F7/00; G03F7/20; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/60; H10D64/00; H10D64/01; H10D64/025; H10D64/027; H10P; H10P14/00; H10P14/40; H10P14/416; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; Y; Y10; Y10S; Y10S148/00; Y10S148/053
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
332 words
A method of manufacturing a semiconductor device, comprising: a first step for forming first, second and third recessed portions at a predetermined pitch on the surface of a semiconductor substrate of one conductivity type by applying an over-exposure and/or an over-development to a portion to be exposed of a positive resist, to allow the dimension of an unexposed portion thereof to be less than resolution, thereby forming said first, second and third recessed portions at a minimum pitch that enables fining or miniaturization to be carried out; a second step of diffusing an impurity of an opposite conductivity type into the first and second remaining regions formed between said first and second recessed portions and between said second and third recessed portions to form an impurity diffused region; a third step of forming an oxide film by heat oxidation, thereafter to apply etching to said oxide film by the etch-back method to form side wall portions of said remaining regions, thus to form a recessed portion of which the width is narrower than those of said recessed portions with the side wall portions being masks; a fourth step of forming an oxide film serving as a gate oxide film over the entire surface; a fifth step of depositing a thin electrode layer to serve as a gate electrode on said oxide film; a sixth step of removing said electrode layer on said first and third recessed portions; a seventh step of depositing an interlayer insulating film over the entire surface; an eighth step of removing said interlayer insulating film on said first and second remaining regions and within said second recessed portion; a ninth step of removing said electrode layer on said first and second remaining regions; a tenth step of allowing a region surrounded by said electrode layer within said second recessed portion to be provided with a conductive layer; and an eleventh step of forming a wire layer electrically connected to said impurity diffused regions and said electrode layer, respectively.
Claim 2
Independent Claim
332 words
A method of manufacturing a semiconductor device, comprising: a first step for forming first, second and third recessed portions at a predetermined pitch on the surface of a semiconductor substrate of one conductivity type by applying an over-exposure and/or an over-development to a portion to be exposed of a positive resist, to allow the dimension of an unexposed portion thereof to be less than resolution, thereby forming said first, second and third recessed portions at a minimum pitch that enables fining or miniaturization to be carried out; a second step of diffusing an impurity of an opposite conductivity type into the first and second remaining regions formed between said first and second recessed portions and between said second and third recessed portions to form an impurity diffused region; a third step of forming an oxide film by heat oxidation, thereafter to apply etching to said oxide film by the etch-back method to form side wall portions of said remaining regions, thus to form a recessed portion of which the width is narrower than those of said recessed portions with the side wall portions being masks; a fourth step of forming an oxide film serving as a gate oxide film over the entire surface; a fifth step of depositing a thin electrode layer to serve as a gate electrode on said oxide film; a sixth step of removing said electrode layer on said first and third recessed portions; a seventh step of depositing an interlayer insulating film over the entire surface; an eighth step of removing said interlayer insulating film on said first and second remaining regions and within said second recessed portion; a ninth step of removing said electrode layer on said first and second remaining regions; a tenth step of allowing a region surrounded by said electrode layer within said second recessed portion to be provided with a conductive layer; and an eleventh step of forming a wire layer electrically connected to said impurity diffused regions and said electrode layer, respectively.
Claim 3
Independent Claim
278 words
A method of manufacturing a semiconductor device, comprising: a first step of forming first, second and third recessed portions at a predetermined pitch on the surface of a semiconductor substrate of one conductivity type; a second step of diffusing an impurity of an opposite conductivity type into first and second remaining regions formed between said first and second recessed portions and between said second and third recessed portions to form an impurity diffused region; a third step of forming an oxide film by heat oxidation, thereafter to apply etching to said oxide film by the etch-back method to form side wall portions of said remaining regions, thus to form a recessed portion of which the width is narrower than those of said recessed portions with the side wall portions being masks; a fourth step of forming an oxide film serving as a gate oxide film over the entire surface; a fifth step of depositing a thin electrode layer to serve as a gate electrode on said oxide film; a sixth step of removing said electrode layer on said first and third recessed portions; a seventh step of depositing an interlayer insulating film over the entire surface; an eighth step of removing said interlayer insulating film on said first and second remaining regions and within said second recessed portion; a ninth step of removing said electrode layer on said first and second remaining regions; a tenth step of allowing a region surrounded by said electrode layer within said second recessed portion to be provided with a conductive layer; and an eleventh step of forming a wire layer electrically connected to said impurity diffused regions and said electrode layer, respectively.
Claim 4
Independent Claim
278 words
A method of manufacturing a semiconductor device, comprising: a first step of forming first, second and third recessed portions at a predetermined pitch on the surface of a semiconductor substrate of one conductivity type; a second step of diffusing an impurity of an opposite conductivity type into first and second remaining regions formed between said first and second recessed portions and between said second and third recessed portions to form an impurity diffused region; a third step of forming an oxide film by heat oxidation, thereafter to apply etching to said oxide film by the etch-back method to form side wall portions of said remaining regions, thus to form a recessed portion of which the width is narrower than those of said recessed portions with the side wall portions being masks; a fourth step of forming an oxide film serving as a gate oxide film over the entire surface; a fifth step of depositing a thin electrode layer to serve as a gate electrode on said oxide film; a sixth step of removing said electrode layer on said first and third recessed portions; a seventh step of depositing an interlayer insulating film over the entire surface; an eighth step of removing said interlayer insulating film on said first and second remaining regions and within said second recessed portion; a ninth step of removing said electrode layer on said first and second remaining regions; a tenth step of allowing a region surrounded by said electrode layer within said second recessed portion to be provided with a conductive layer; and an eleventh step of forming a wire layer electrically connected to said impurity diffused regions and said electrode layer, respectively.
Claim 5
Dependent Claim
37 words
A method of manufacturing a semiconductor device as set forth in claim 1, wherein said electrode layer is formed of a polysilicon layer, said polysilicon layer being disposed in said recessed portions on said gate oxide film.
Claim 6
Dependent Claim
77 words
A method of manufacturing a semiconductor device as set forth in claim 1, wherein after said gate electrode of said fifth step is formed of a relatively thin polysilicon layer, said gate oxide films on the impurity diffused regions are removed, and tungsten layers are deposited on said polysilicon layer within said recessed portions and on aid impurity diffused regions, respectively, thus allowing said recessed portion on said polysilicon layer to be provided with said tungsten layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-03 | 1995-09-02 | 1996-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-03 | 1999-09-02 | 2000-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-03 | 2003-09-02 | 2004-03-03 | $7700.00 | Window Closed / Lapsed |