Semiconductor topography for a high speed MOSFET having an ultra narrow gate

Abstract

Abstract A semiconductor topography for a transistor having an ultra-narrow gate conductor. A method for forming the semiconductor topography may include etching a patterning layer extending across a conductive gate layer to form an opening extending to an upper surface of the conductive gate layer. Subsequently, a masking layer is formed upon the exposed upper surface of the conductive gate layer. The patterning layer and portions of the conductive gate layer not shielded by the masking layer are then removed to form a gate conductor. Lightly doped drain impurity areas may then be formed in the semiconductor substrate aligned with sidewall surfaces of the gate conductor. In an embodiment, spacers may be formed adjacent sidewall surfaces of the gate conductor substantially simultaneously with removal of the masking layer and portions of a gate dielectric layer not shielded by the gate conductor. Source and drain impurity areas may then be formed in the semiconductor substrate aligned with sidewall surfaces of the spacers. A metal silicide may be formed upon upper surfaces of the gate conductor and the source and drain areas.

Inventors

• 👤 Mark I. Gardner
• 👤 Frederick N. Hause

Bibliographic Details